Wishbone High Performance Z80

Wishbone High Performance Z80


Category: Processor

Created: March 04, 2004

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: Yes

WishBone version: n/a

License: n/a


The purpose of the Wishbone Z80 development is to provide a “low-end engine” (written in verilog) that could logically interface with many of the low-end verilog peripherals available to the community, while providing sufficient “horsepower” to be used effectively with the more interesting “high end” peripherals.

The deign is conceived to operate efficiently with internal static RAM. Thus, a two stage pipeline is implemented to allow instruction execution at the access rate of a 32 kbyte RAM. (This could be well over 300 Mhz. depending on implementation technology.)