S1 Core - 64-bit SPARC v9 Core with Wishbone Master Interface

S1 Core - 64-bit SPARC v9 Core with Wishbone Master Interface

Details

Category: Processor

Created: January 03, 2007

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: Yes

WishBone version: n/a

License: GPL

Description

S1 Core briefly...

The S1 Core is a reduced version of the OpenSPARC T1 released by Sun Microsystems. While the T1 is a complete microprocessor with 8 cores (capable of running up to 32 concurrent threads) and includes a crossbar switch, L2 Caches and several other interfaces, the S1 takes only one 64-bit SPARC v9 core (capable of running from 1 up to 4 concurrent threads) and includes a Wishbone Master Interface to connect to the cores available on OpenCores.

In recent years the project has not been actively worked on, so users are strongly advised to use Princeton University's OpenPiton project instead: http://parallel.princeton.edu/openpiton/