Zorro Bus to Wishbone Bridge

Details

Category: System on Chip

Created: Jun 23, 2010

Updated: Jan 27, 2020

Language: Verilog

Other project properties

Development Status: Planning

WishBone compliant: Yes

WishBone version: n/a

License: LGPL

Download Core Submit Issue

Description

This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at the same time on the same bus. I suppose this will really end up being two bridges, one for each direction.

I am learning Verilog RTL for SoC/ASIC design and testbench simulation at work, and I think this will be an interesting "other than my day job" project to gain more experience with Verilog coding, tools, FPGA boards and FPGA tools. I also think that the Amiga in an FPGA community will benefit from gaining access to the numerous Wishbone peripheral cores here at opencores.org.

This project will be based on Zorro bus documentation as found in

the Commodore Amiga A3000T Service Manual
the Commodore-Amiga Inc. Zorro III Bus Specification rev 1.10
the Commodore Amiga A500/A2000 Technical Reference Manual
the Commodore-Amiga Inc. Amiga Hardware Reference Manual 3rd Edition
and other service manuals that seem relevant in my collection.

,
,
,he can be found on utilitybase,
,
,
,
,
,

as a Zorro slave peripheral card plugged into an Amiga motherboard Zorro slot
as a Zorro bus master peripheral card plugged into an Amiga motherboard Zorro slot
as a Zorro system controller on some motherboard which is in control of that motherboard's various Zorro slots (ie. it watches all busmaster acknowledge signals from all slots, sends busmaster grant signals to all slots, determines which acknowledge to send and when, etc. which are beyond a peripheral busmaster card's responsibilities) This is the mode which will be interesting to people wanting to add Zorro slots to the open-sourced MiniMig Amiga in an FPGA project as one example, as the system needs more control capabilities than a busmaster peripheral does. This is also the mode of interest if anyone wishes to create a replacement for Commodore's SuperBuster system bus controller chip.

Phase 1:	Implement Zorro II / Zorro III slave peripheral mode to Wishbone master bus. This allows connecting a Wishbone slave peripheral to a Zorro host system. (Zorro slaves may be able to DMA into the host system under direction from the host system driver software, but will not be able to request control of the bus) Phase 1a will be ZorroII host/master to Wishbone peripheral/slave Phase 1b will be ZorroIII host/master to Wishbone peripheral/slave
Phase 2:	Implement Zorro II / Zorro III busmaster peripheral mode to Wishbone slave bus. This allows connecting a Wishbone master bus/peripheral to a Zorro slave. This should allow two uses: Wishbone master peripheral on a Zorro busmastering peripheral plugin card, inserted into a Zorro host system. Phase 2a ZorroII host to Wishbone master peripheral Phase 2b ZorroIII host to Wishbone master peripheral Wishbone host system can use one, possibly multiple Zorro slave peripheral plugin cards, but no Zorro busmastering peripheral plugin cards. (busmaster capable Zorro cards should work fine as slaves, and may be able to DMA into the host system under direction from the host system driver software, but will not be able to request control of the bus due to lack of Zorro bus arbitration logic) Phase 2c Wishbone host to ZorroII master peripheral Phase 2d Wishbone host to ZorroIII master peripheral
Phase 3:	Implement Zorro II / Zorro III system bus controller mode, which adds in Zorro bus arbitration logic. This will allow a Wishbone host system full use of all Zorro slave and busmaster peripheral plugin cards to request control of the bus and DMA into the host system. It's possible that this may be little more than pairing Phase 2 with an existing OpenCores or other suitable arbiter. I think it should be desirable to reuse as much existing IP as possible. (with compatible licensing of course)

,
,
,

A small adapter board will allow the 100pin Zorro edge connector to fit onto this FPGA board's PCI edge connector when testing slave and busmaster peripheral modes in an Amiga 3000 desktop and/or A4000T computer. Host Amiga computer will use a SuperBuster rev 11 system bus controller chip to control its Zorro bus. I need to verify that the PCI edgecard on my Spartan3 board can be treated this way, or if the onboard levelshifting groups prohibit direct Zorro slot compatibility.
Another adapter board will be made to provide a connection to an Amiga 4000 desktop computer's Zorro backplane daughterboard, possibly also the Amiga 3000 desktop computer's equivalent if supporting both is reasonable. This easily provides for a number of Zorro slots while reducing PCB board design on my part. Testing in this mode will likely include aoOCS and porting the MiniMig, DragonBall/68K Wishbone interface, and ao68000 or ae68 cores to my evaluation board. This combination should give me a Wishbone Minimig core attached to a Wishbone CPU, everything in verilog, where the traditionally Minimig-paired TG68 is a VHDL non-Wishbone CPU. A single HDL language should make life easier on me, as will existing Wishbone CPU and interface to Minimig's 68000 bus. Again I need to verify that the level shifting groupings on the Spartan3 board allow direct Zorro bus connection.
Any adapter PCBs will be open-sourced as part of this project, and will be in Eagle schematic/board file format.