Arithmetic logic unit (ALU) with selectable inputs and outputs

Arithmetic logic unit (ALU) with selectable inputs and outputs


Category: Uncategorized

Created: January 24, 2007

Updated: January 27, 2020

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a


A didactical project in Verilog. It's about a core containing an ALU with selectable inputs and outputs. The design itself will be suited for Verilog beginners willing to make the next step by building a circuit having practical requirements and that is a little more complex than the ones presented in Verilog books. In the end, the users will have tested all the operator types and operator symbols existing in Verilog and will have closely observed the way Verilog performs operations with the provided operands.
The source code will also contain tests, ranging from direct tests and random tests to improved tests. I will present the advantages and disadvantages of each one of them. Improved tests will be a very good introduction to design verification concepts like BFMs, monitors, collectors and checkers. These verification environment components will be written in/adapted to Verilog, since a design verification language (DVL) like Vera is not widely used in technical universities or even more, not at home.


- selectable inputs and outputs
- serial input and output data
- ALU performing all known Verilog operations
- Verilog verification environment included
- introduction to verification entities like BFMs, monitors, collectors and checkers


- finished, there is room for improvement