Keyboard Controller with Simple Debounce Algorithm

Keyboard Controller with Simple Debounce Algorithm


Category: Uncategorized

Created: July 01, 2005

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: GPL


The controller scans the keyboard by making a different column in "rows" logic-0
therefor the inputs "cols" have to be PULL-UP high. It processes the inputs "cols" and
the newly found keychange (keypress or keyrelease) is converted to the corresponding
scancode (translated set2). Note that an interrupt pin is attached as well to make it
possible to connect this controller to a PIC.

Also note that the keyboard_controller uses an internal clock divider to divide
the system clock of 50 Mhz to 100 kHz. Should you want to use an other frequency
than 100 kHz please do not forget to change Constants.vhd


- Simple debounce algorithm, it checks for stable inputs in last #nr samples
- Ghosting protection
- Module is easy to understand and build out of sub-modules


- Currently used for input processing of a toy-keyboard