Cray-2-Reboot for FPGAs
Details
Category: Uncategorized
Created: July 06, 2016
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
Additional info: Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Files also located at: https://github.com/DarkwaveTechnologiesCray-2-Reboot
The goal of this project is to make a clock and gate equivalent recreation of a Cray Research Cray-2 supercomputer that will run on an FPGA board. Resources permitting, a small IC run using MOSIS or CMP will be the stretch goal for the project.
This project will be made of a number of phases:
1) Conversion of module logic to working Verilog code
2) Cleanup of Verilog code
3) Interconnecting all the Verilog together into a functional machine
4) Software emulation of the Verilog code for verification
5) Recovery and/or creation of basic OS & C compiler for the system (c complier will likely be a translated version of TCC)
6) Testing on FPGAs