Datetime
Details
Category: Uncategorized
Created: June 15, 2012
Updated: November 19, 2019
Language: Verilog
Other project properties
Development Status: Planning
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This is a date/time keeping core. It uses an external 100,60 or 50 Hz time-of-day signal to update a group of BCD counters which record the date and time. The date and time is presented as a 16 digit BCD format YYYYMMDDHHMMSSJJ which fits into a 64-bit word.
Features
- optional 50,60, or 100 Hz time-keeping
- 64 bit bus interface
- internally decoded to respond in address range $DC0400-$DC0418
- Mars timekeeping option (millennium style calendar)
- leap year tracking
- independent system bus and time-of-day clocks
- alarm setting