Discrete Wavelet Transform Co-processor on Still Image
Details
Category: Uncategorized
Created: December 23, 2004
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Beta
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
This core implements Forward and Inverse Discrete Wavelet Transform (FDWT and IDWT) on still image. Wavelet LeGall 5/3 is selected in design. The project is simulated on ModelSim 5.7g and going to implement on Spartan-3 Starter Kit.
Status
11/10/2004: started
20/12/2004: Core is correctly simulated on Lena image (512x512).
