I2C Slave For Data Transfer

I2C Slave For Data Transfer Click to expand image


Category: Uncategorized

Created: March 01, 2004

Updated: November 19, 2019

Language: Other

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a


This is the first version of a simple I2C slave for 8 bit data transfer written in Verilog.
Two pull-up resitors needed for SDA and SCL lines.
Any comment and further elaboration is welcomed.