DragonBall/68K Wishbone Interface
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Details
Category: Uncategorized
Created: December 02, 2002
Updated: November 19, 2019
Language: Verilog
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: n/a
Description
This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus.
Features
- 16bit Motorola DragonBall/68K Interface
- 16bit full featured RevB.3 Wishbone Classic Master interface
- programmable address-bus size
- static synchronous design
- fully synthesisable
- 6LUTs in a Spartan-II, 32LCELLs in an ACEX
Status
Design is finished and available in Verilog for download from OpenCores CVS.
