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Details
Category: Uncategorized
Created: May 31, 2008
Updated: Jan 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
This project contains a Basic and generic UART SerDes controller.
Configuration:
-Enable/Disable Odd/Even parity bit
-bit stop number Enable/Disable
-baud rate selection
*1200
*2400
*4800
*9600
*19200
*38400
*57600
*115200
*230400
*460800
*921600
Note:
Br*br_divisor=921.600
Fclk/921.600=clk_divisor
=> Br=Fclk/(clk_divisor*br_divisor)=1/((clk_divisor*Tclk)*br_divisor)
