CDC Micro FIFO Click to expand image


Category: Uncategorized

Created: December 02, 2010

Updated: November 19, 2019

Language: Verilog

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: BSD


Clock Domain Crossing micro FIFO (Verilog/SystemVerilog):
cdc_ufifo provide an minimalist fifo. Most advantage - not use RAM blocks.
it can be 4 buffer data cells minimum.
by default used implementation without ram, only standart register cells used, and it can be selected if need. most slowest stage is the output multiplexor
Shadowed outputs: provide an register after multiplexer to remove data unsynchronized changes from outputs when skiped some cycles.


CycloneII project works on up to 50 MHz data transfers