GCC Compiler for OCMIPS
Created: September 10, 2007
Updated: January 27, 2020
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
GCC Compiler for OCMIPS
I built the GCC compiler for ocmips using the cross tool scripts written by Dan Kegel, you can download the scripts from
http://kegel.com/crosstool/crosstool-0.43/doccrosstool-howto.html (Thanks for Zhangfeifei's ucore project to tell this)
to build a cross tool chain. I try it in both Cygwin and Linux.
Final exe files in cygwin environment is offerd in directory of tools. You can wirte windows batch command to use it, example bat files is given in directory of test.
Currently, MIPS assemblly can be compiled by ASM compiler in tools directory in Windows system using bat command, but C files can NOT be compiled by GCC compiler(exe file) offered in tools directory using bat files in Windows system. I don't know why, maybe some cygwin files is needed.
Anyway, comile C program directly in Linux or Cygwin using make has no problems.
The ocmips CPU core is compatible with MIPS32 instruction set.It uses havard architecture which has different instruction and data memory. It is pipelined with six stages. It has been tested with a lot of C programs which compiled by GCC for mips compiler, and no bugs were found.
Currently, interrupt is not supported because my spare time is limitted. Everyone interested with this core can help to add it. I think it is not very hard to add interrupt logic to the core, because the architecture and verilog code of ocmips is very clear and it is easy for you to understand it.
The CPU core is implemented in VerilogHDL and tested on a Xilinx FPGA(XC3S400) running at 50 MHz (synthesized maximal clock using Synplify is 82MHz @ Xilinx Spartan 3 xc3s400 technology).
All the source code will be uploaded in a few days, if you are urgent, please email me freely!
Advancd Version of OCMIPS
There are advancd version of OCMIPS which contains write-through data cache and reconfigrable branch predictor (multiply and divide inst. NOT implemented). This version of ocmips is being tested on FPGA board, but it has already pass functional simulation.
Any help and enhance of performance to OCMIPS will be appreciated. Please contact me freely, my email address is BraydenHsueh@gmail.com.
MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. Xue Bo are not affiliated in any way with MIPS Technologies, Inc.
Soft Simulator in C
A soft simulator which based on Plasma project's of opencores is also given. It adds cache and branch predictors, and also a function named "readelf()" is also added so that this simulator can directly accept ELF file.
Call for New Maintainers and Developers
Any help will be appreciated, especially in enhancing performance, test , improvment on constructing GCC compiler and analysis of ELF files.
FPGA Verification Result