Pulse Width Modulator with 16-bit Main Counter
Details
Category: Uncategorized
Created: September 19, 2012
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
Pulse Width Modulator
Features
• Work as one PWM or one timer.
• 16 bits main counter.
• PWM/Timer can choose between Wishbone interface clock or external clock as working clock.
• PWM can choose between dedicated duty cycle input or internal register as source of duty cycle.
• Duty cycle and period can be changed at runtime.
• Hosted through Wishbone slave interface.
• Working clock's frequency can be divided to at most 1/65535 of original frequency.
• Period register also serves as timer target register when module is in timer mode.
