Random Pulse Generator
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Details
Category: Uncategorized
Created: March 26, 2015
Updated: November 19, 2019
Language: Verilog
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Poisson process generator. The time between each pair of consecutive pulses has an exponential distribution with desired rate. Тhе auxiliary pseudo-random uniform generator is based on 32-bit LFSR. The deign is tested on MICROSEMI IGLOO2 FPGA.
Histogram of the number of clocks between output pulses:
