SystemC to Verilog Synthesizable Subset Translator

SystemC to Verilog Synthesizable Subset Translator

Details

Category: Uncategorized

Created: October 08, 2004

Updated: January 27, 2020

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: n/a

Description

The sc2v translator is a software tool that translates a SystemC RT description into a Verilog equivalent one.
The sc2v translator is based on lex and yacc tools.
You need lex and yacc installed in order to compile sc2v.


This work is given by Universidad Rey Juan Carlos (Spain)
www.gdhwsw.urjc.es

Status

- Version 0.5
- TODO: See README File

- LOOKING FOR CONTRIBUTORS