JPEG Encoder Using Baseline Encoding Method

JPEG Encoder Using Baseline Encoding Method

Details

Category: Video Controller

Created: March 07, 2009

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: Others

Description

Features

• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1
• Standard JFIF header v 1.01 automatic generation
• Color images only (3 components, RGB 24 or 16 bit, YUV input)
• Two programmable Quantization tables
• Hardcoded Huffman tables (luminance and chrominance)
• 2.3 to 2.7 clock cycles per one input 24 bit pixel @ 50% Quality
• OPB programming and data Host interface
• 4:2:2 subsampling
• Source code target independent, synthesizable RTL VHDL code
• Detailed documentation

Throughput

Example throughput

Measured from JPEG encoding start till encoding done:

• Input image 640x480 24 bit RGB color. New sample loaded every cycle until FIFO full.
• Quantization tables at 50% quality setting
• 7.3 ms processing time @ 100 MHz clock
• 1000/7.3=136 frames per second @ 100 MHz
• Input file size = 921 kB. Output file size = 44 kB (depends on image)

Compression stats (from JPEGSnoop software):
• Compression Ratio: 21.31:1
• Bits per pixel: 1.13:1

100 MHz is achievable under Stratix II S90 for example. Optimization set to performance.

 

TODO

• replace OPB interface used for programming with PLB or WishBone

 

AREA/PERFORMANCE

Device Utilization Summary for Stratix II S90 (mkjpeg revision 57)

6135 ALUTs
3095 registers
3858 ALMs
4 DSP9
55 M4K
1 MRAM

Performance: above 100 MHz

Build configured for maximum image width 640 pixels and highest performance and memory usage (settable in JPEG_PKG.VHD)