Facebook
Google
GitHub
LinkedinSimulated and Synthesized Wishbone Out Port From B3 Spec
Details
Category: System on Chip
Created: Jan 27, 2008
Updated: Jan 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
Additional info: Design done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
Are you using Wishbone, do you need some simple 'slaves' to test your bus with ?
Well, the Wishbone spec, appendix B3, has VHDL examples of Wishbone outports, and memories.
This is the code from B3 ! saves one copying the PDF each time.
Features
- Can be simulated and can be synthesised.
Status
Simulated in XST 9.2 sp 4
Synthesised to Spartan FPGA.
