The 2021 RISC-V Summit Charts the Wildfire Expansion of Open-source Hardware

December 10, 2021 by Tyler Charboneau

If 2021's RISC-V Summit told us anything, it's that the open-source hardware movement isn't slowing down anytime soon.

With this year’s RISC-V Summit officially concluded, open-source processors are being adopted faster than ever. Membership in RISC-V International has grown by 130% in 2021 alone—and individual contributors have enthusiastically chipped in. What has the electrical-engineering community achieved throughout the past 12 months with RISC-V? 


A Year of Growth

This year’s conference highlighted yet another period of explosive growth for the RISC-V ISA and the association’s membership. RISC-V International is now 2,478 members strong while working groups and committees account for nearly 12,000 individual members. Over 70 countries are represented. 

This support signals a growing investment in the organization’s mission, which is “to deliver a new level of free, extensible software and hardware freedom on architecture.” Accordingly, RISC-V estimates that two billion RISC-V cores will exist within the market this year. These exist across multiple industries and applications—like automotive, 5G, AI, and others. The open standard is intended to democratize chipset design. 


Comparison of processor ISAs

Comparison of processor ISAs. Image used courtesy of Tirias Research and Forbes

Additionally, RISC-V International hopes to gain a greater piece of the processor IP market share. This is currently dominated by Intel x86, AMD, and Arm. These major players—RISC included—have their own licensing structures that determine fees and conditions for usage.

RISC-V is attractive in that its commercial license helps generate some profits (through microarchitecture) for the association, yet it still offers a free open-source IP license. Users are never charged any Instruction Set Architecture (ISA) fees. This helps boost adoption. 


Specifications and Alliances Aplenty

Specifications dictate how teams should design their chips in accordance with specific applications, like edge computing or data processing. In this way, they serve as best practices—much like the OpenAPI Specification (OAS) does for APIs. An evolution of these specifications over time is an indicator of developmental health.

This year, RISC-V members ratified 15 new specifications and over 40 extensions. New specifications center on these emerging focus areas:

  • ML inference for audio, visual, and voice
  • Complex data array processing
  • Multi-type hypervisor and virtual machine (VM) implementations
  • Cloud-native applications related to automotive, data centers, and industrial controls
  • IoT and embedded devices
  • Security through cryptographic hashing and block ciphering

There are currently three core specifications: the ISA Specification, the Debug Specification, and the Trace Specification. These cover design (hardware and software), troubleshooting, and live device profiling. Finally, the Compatibility Test Framework is useful for determining baseline performance and compliance. 


A High-level Glimpse of the 2021 RISC-V Summit

During the Summit’s three-day runtime, members had the opportunity to give keynote speeches, lead breakout sessions, and expositions. The latter was where each presenter demonstrated a new technology or touted their development progress to audiences. Major sponsors included big names like Western Digital, Siemens, the CNCF, Microchip, Imperas, and the Linux Foundation. 



Block diagram of the "world's first" RISC-V-based SoC FPGA. Image used courtesy of Microchip (PDF)

Numerous presenters spoke on the following topics—while offering a glimpse into the fruits of their RISC-V R&D endeavors: 

  • Scaled AI-and-ML acceleration, plus extensibility
  • RISC-supported open hardware for open-cloud applications
  • Building RISC software ecosystems
  • Heterogenous virtualization architectures and cores
  • The software-hardware relationship for performance-based workloads
  • Security and galvanization in autonomous and cloud applications

Each day spanned 9.5 hours, accounting for breaks. The breadth of information was vast, and over 94 sessions of varying length and technical depth took place. The RISC-V Summit was also a hybrid event. Attendees could physically visit the San Francisco venue, or tune in from the comfort of home. Accordingly, many session recordings are available on the official website


RISC-V Advances Railways, EVs, and Quantum Computing

A number of interesting innovations have emerged this year based on RISC-V. IAR Systems has debuted new RISC-V development tools aimed at IEC 61508 and ISO 26262 certification. These outline procedures for developing RISC-compatible medical devices, European railway standards, household appliances, and more. 

We also know how promising the EV and AV markets will be in the coming decade. Renesas and SiFive are jointly releasing high-end RISC-V solutions for automotive applications. These are described as next-gen, though they could potentially have viability within final generations of pure ICE-powered vehicles. 

What about quantum-computing advancements? A Technical University of Munich (TUM) team has designed and launched the production of a post-quantum cryptography chip. This could protect future systems against hackers—whether those hackers target or employ quantum hardware. 

Three other major announcements at the Summit captured headlines. 


The “World's Fastest”  Licensable RISC-V Processor IP Core

At the event, RISC-V pioneer SiFive announced what it termed the “world’s fastest licensable RISC-V processor IP core.” The new Performance P650 processor comes just months after the Performance P550 processor, outperforming its predecessor by 40% (per clock cycle). SiFive claims the P650's performance even trumps the Arm Cortex-A77.  


Diagram of the Performance P650 series

Diagram of the Performance P650 series. Image used courtesy of SiFive

The company projects that the P650 scores a performance rating of 11+ SPECInt2006/GHz, making it equipped for high-end computing applications from mobile edge processing to data center computing. The device can be scaled to 16 cores using a so-called coherent multicore complex. This includes system components ranging from memory management to interrupt unit control, which enables the RISC-V hypervisor extension necessary for virtualization. 

Dr. Yunsup Lee, SiFive's co-founder and CTO, explained that this rollout fulfills the company's mission “to answer the semiconductor industry’s call for more processor IP choices.”


SEGGER's Embedded Studio Supports 64-bit RISC-V CPUs

Another announcement at the RISC-V Summit came from SEGGER with an update to its legacy Embedded Studio. Now, the program supports 64-bit RISC-V processors while integrating several of SEGGER's programs for code generation. 


Some of the newly-supported CPUs

Some of the newly-supported CPUs include the RV64I, RV64E, and RV64GC with floating-point units. Image used courtesy of SEGGER

Embedded Studio integrates a debugger that can support a simulator for automated testing. It also includes GDB remote protocol, so designers have flexible options for debug probes. J-Link, the debug probe commonly used for Embedded Studio, also supports standard 32- and 64-bit RISC-V cores. 


Imagination Unveils a New RISC-V CPU Line

As a testament to RISC-V's expansion, Imagination Technologies released a new RISC-V-based CPU product line designed for heterogeneous computing. This open-source architecture dubbed “Catapult” comes in multiple configurations—specifically in the form of four families: microcontrollers, real-time embedded CPUs, high-performance CPUs, and automotive CPUs.


Block diagram of Catapult

Block diagram of Catapult. Image used courtesy of Imagination Technologies

With offerings in both 32-bit and 64-bit variants, the Catapult line is multi-threaded and can be scaled up to eight asymmetric cores per cluster. This, Imagination claims, allows customers to add custom accelerators while also enhancing an SoC's versatility. 

Because this new line of CPUs is compliant with the RISC-V ISA, customers can tap into the ever-broadening RISC-V ecosystem, including development tools and software. 


RISC-V Blazes Forward

RISC-V continues to gain steam thanks to its open-source nature, performance benefits, security focus, and political aversions. The 2021 Summit demonstrates the global reach of RISC-V International. 


The RISC-V Foundation's initiatives moving into 2022

The RISC-V Foundation's initiatives moving into 2022. Image used courtesy of the RISC-V Summit 2021

Companies have the ability to solely run with the RISC-V ISA, yet there’s a major incentive to partner with other organizations. This, combined with new training and mentorship opportunities, will bring new products and services to market even faster. 



Featured image used courtesy of the RISC-V Summit 2021.