What Is Power Sequencing?
Systems such as CPUs, DSPs, and FPGAs often require multiple power rails. With a multi-voltage and/or multi-processor system, we have to turn the power supplies on/off with an appropriate timing. This controlled power-up/power-down cycle is called power supply sequencing. For example, in a multi-voltage microprocessor, we may have to power up the I/O power supply before turning on the core, itself. As another example, consider a CPU operating a graphics controller. We may have to power up the CPU before the graphics display so that we can avoid uncontrolled outputs on the graphic display.
To gain some insight, consider the simple power sequencing technique shown in Figure 1. In this figure, both “Device 1” and “Device 2” are connected to the same supply rail. However, the RC circuit will make VCC2 a delayed version of VCC1 and, hence, “Device 2” will turn on some time after “Device 1”. This technique has several limitations and, in practice, we’ll have to use more sophisticated methods such as those discussed in Power-Supply Sequencing for FPGAs and Power Supply Sequencing Simplified.
Figure 1. Schematic of a simple power sequencing technique. Image courtesy of Maxim Integrated.
The Analog Devices ADM1266 Sequencer
In a complex system, we may need to sequence more than 10 power supplies. In these cases, a single-chip programmable sequencing solution such as the Analog Devices ADM1266 can facilitate power supply sequencing and monitoring. The functional block diagram of the ADM1266 is shown in Figure 2 below. In the rest of the article, we’ll look at some of the most important features of this device.
Figure 2. The functional block diagram of the ADM1266. Image courtesy of Analog Devices.
Supply Fault Detectors
A single ADM1266 can monitor and sequence up to 17 supplies. This is achieved by a bank of Supply Fault Detectors (SFD) that is depicted on the left side of the above functional block diagram. There are a total of 17 SFDs. Each of these SFDs is used to monitor one dedicated input of the device labeled as VH1 to VH4 and VP1 to VP13 in the figure. The block diagram of an SFD corresponding to a VHx input is shown in Figure 3.
Figure 3. The block diagram of an SFD corresponding to a VHx input. Image courtesy of Analog Devices.
As you can see, the SFD incorporates two comparators. The threshold value of these comparators is programmable. If the input voltage rises above the programmable threshold of the overvoltage comparator or it goes below the programmable value of the undervoltage comparator, the SFD will issue an overvoltage or an undervoltage fault, respectively.
Additionally, the output of a comparator goes through a programmable glitch filter. In this way, we can remove the spurious transitions of the comparator output that has a duration less than a programmable value.
Note that the SFDs connecting to the VPx inputs are a little bit different and allow precision differential voltage measurement on the VPx inputs.
Programmable Sequencing Engine (SE)
The ADM1266 has a programmable sequencing engine that allows us to control the outputs of the device, i.e., the GPIO and PDIO pins in Figure 2. The SE implements a state machine which responds to the events driven by the VHx and VPx inputs, GPIO and PDIO outputs, and the device timers and variables. The events are fed into the SE to determine the GPIO and PDIO states. This allows us to generate the power-up and power-down sequence required by a particular application.
Note that a single ADM1266 can monitor and sequence up to 17 power supplies; however, it’s possible to operate several ADM1266 devices in parallel to sequence up to 257 supplies. To accommodate such complex sequencing scenarios, the ADM1266 supports state machines incorporating up to 1,023 states. The state machines can be created using the Analog Devices Power Studio software. The software will compile the virtual state machine defined by the user to generate the state machine for each ADM1266 device in the system.
The ADM1266 incorporates internal DAC units that can be used to perform supply (or voltage) margining.
What is “voltage margining”?
Generally, the term “voltage margining” is used to refer to tests in which the supply voltage of a system is changed slightly to make sure that the system performance is still acceptable. We may change the power supply of the system by 5%, about its nominal value, and evaluate the system performance once the supply voltage has settled at the margined voltage. You can find details of voltage margining in Voltage Margining Made Easy and Plug-In Modules: Understanding Margining and Prebias Start-Up.
Voltage Margining in the ADM1266
As explained above, the general concept of voltage margining refers to the end-of-line testing to assure rated performance in the presence of supply voltage variation. However, the ADM1266 datasheet suggests applying the voltage margining concept to increase the accuracy of a power supply by compensating for the tolerances in components and voltage reference levels. The idea is illustrated in Figure 4 below.
The dedicated inputs of the ADM1266 are multiplexed to an on-chip 12-bit SAR ADC. After going through a “Control Block”, the output of the ADC is converted to an analog signal. The DAC output is applied to the feedback node of the power supply which is a DC-to-DC converter. This forms a feedback loop that senses the output voltage of the DC-to-DC converter and applies an appropriate signal to the “FEEDBACK” input of the power supply. Appropriately modifying the “FEEDBACK” node, the loop can increase the accuracy of a power supply.
Figure 4. Voltage margining as a way to increase power supply accuracy. Image courtesy of Analog Devices.
As shown in Figure 2, there are nine on-chip DACs in an ADM1266 device. Hence, margining is possible on nine rails.
Black Box Fault Recording
The ADM1266 supports a black box feature that can store the status of the system when a black box write operation is triggered. For example, when all the input supplies fail, we can trigger a black box write to save the system status. We can even use the real-time counter (RTC) of the ADM1266 to save the time when a black box write operation is triggered. These features can be helpful in debugging system problems.
Note that when multiple ADM1266 devices are working in parallel, we can use an external crystal to generate the time base for one of the ADM1266 devices and use the “SYNC” pin of this device to synchronize the other devices. This is shown in Figure 5.
Figure 5. Multiple ADM1266 devices in parallel utilizing one external crystal in and inter-pin synchronization to generate base time. Image courtesy of Analog Devices.
As shown in Figure 2, the ADM1266 has a logic block that is independent from the SE and margining sections. The logic block consists of programmable logic elements such as AND, OR, etc. The user can cascade these basic logic functions to implement an arbitrary combinational logic. The inputs to this block can be a combination of PDIOs, GPIOs, and the SFD faults. The output of the logic block can be assigned to a PDIO or GPIO.
PMBus Digital Communication
The ADM1266 supports Power Management Bus (PMBus) which is a two-wire communication protocol based on I2C. The protocol defines a set of generic commands for power management systems. However, based on the requirements of a given application, each manufacturer can add certain commands to the generic PMBus commands.
The ADM1266 uses the PMBus commands for various purposes such as margining, setting the black box parameters, sequencing, etc. You can find the list of the supported commands in the device datasheet.
EVAL-ADM1266 Evaluation Board
Analog Devices has developed an evaluation board for the ADM1266 that is shown below.
Figure 6. Image courtesy of Analog Devices.
In this article, we looked at some of the important features of the ADM1266. Do you have examples of how you utilized power sequencing in the past? Do you have any experience with the ADM1266 or other similar parts? Please let us know in the comments below.