DARPA has been a powerful force in the electronics industry, particularly in funding research by awarding large contractor deals. Through programs like IRIS (Integrity and Reliability of Integrated Circuits), DARPA has developed methods to detect counterfeit ICs and determine their trustworthiness. It's also been instrumental tackling security issues in conjunction with programs like TRUST. Such programs represent a concerted effort by the best-funded military on earth to address various issues arising in the tech industry.
The six new programs announced will see $216 million in funding for the 2018 fiscal year, and even more invested over the next four years, to support research in three pillars: circuit design tools, advanced new materials, and system architectures for microelectronics.
Image courtesy of DARPA.
This comes at a time when Moore’s Law begins to reach its limitations, a law which projects that every two years the number of transistors on a silicon chip will double. As time moves forward, fitting more transistors onto a chip is becoming more difficult in terms of manufacturing, tolerances, and changes in behaviors of electronics when transistors are so densely packed together.
These research initiatives will focus on areas where scaling is no longer sufficient in increasing performance while decreasing cost and will build off of already existing DARPA initiatives, including JUMP (Joint University Microelectronics Program).
Image courtesy of DARPA.
The new programs will each answer a specific question (referred to as a "thrust") described in the official announcement:
Focus on Material Sciences
Can we use integration of unconventional electronics materials to enhance conventional silicon circuits and continue the progress in performance traditionally associated with scaling?
3DSoC: Three-Dimensional Monolithic System-on-a-Chip
The answer the above question, the 3DSoC program will focus on building up, extending microsystem fabrication on a single substrate for microelectronic chips from 2-dimensional formatting, to 3-dimensional formatting. This could decrease the size of such chips and increase logic density.
FRANC: Foundations Required for Novel Compute
The FRANC program seeks to overcome the impact that the separation of memory and logic has on computation time and performance. In the traditional Von Neumann architecture, time and resources must be used to move data between these two components. A new way to handle memory and logic (whether through new types of components, algorithms, or materials) could help decrease or eliminate this lag and speed up performance.
3-dimensional stacking on an SoC. Image courtesy of Qualcomm.
Designing Modern SoCs
Can we dramatically lower the time and complexity required to design modern SoCs, and unleash a new era of circuit and system specialization?
IDEA: Intelligent Design of Electronic Assets
The goal of the IDEA program is to develop a "no-human-in-the-loop" framework that will allow the design of complex electronics within 24 hours. A significant amount of time, skills, and a wide domain of knowledge is typically needed in such an endeavor. By having this platform made available, producing new systems will become quicker and more efficient.
POSH: Posh Open Source Hardware
The POSH program is the other side of the token of the IDEA program—this will see the development of an open-source platform to verify complex electronic systems, to allow for the focus on design to be more application based.
Can we enjoy the benefits of specialization in the chip but still rely on general programming constructs?
SDH: Software Defined Hardware
With the expectation that reconfigurable hardware will be critically important for machine learning applications, such as autonomous driving, the SDH program will focus on technology for decision-assistance in the design of reconfigurable software and hardware systems being used for data-intensive algorithms. Systems that will eventually be used for things autonomous driving will be making decisions on large quantities of data coming in from sensors in real-time, and so a well-developed platform will be important.
DDSoC: Domain-Specific System on a Chip
The DDSoC program will support the development of a single platform that can be used to program SoCs that comprise of general-purpose hardware, application-specific hardware, different memory components, and I/O components. This will eliminate having to handle each component separately and speed up the design process.
The proposal days for each thrust were all scheduled in the first half of September, so keep an eye out to see what research will be following! If you'd like to learn more about previous DARPA programs, you can search their research archive.
Feature image courtesy of DARPA.