Arteris Revs New Version of Its Cache Coherent Interconnect IP

March 13, 2024 by Jake Hertz

Launched today, the new network-on-chip IP improves SoC performance by streamlining coherent communication between various SoC components.

Today, Arteris announced the newest version of its cache coherent network-on-chip (NoC) IP. Cache coherency, essential in multi-core and distributed computing systems, ensures all units have access to the same data at the same time. This mechanism is especially important in safety-critical applications, like modern automobiles, in which dozens of different processors and memory units are scattered throughout the vehicle's body. 


Ncore deployed in a SoC

Ncore deployed in a SoC


The latest iteration of Ncore allows hardware accelerators to be quickly integrated into a coherent domain, making SoC design faster and more efficient. Arteris claims that SoC design teams accustomed to manually generating interconnect systems can save up to 50 years of engineering effort per project with its building-block approach. 

All About Circuits sat down with Frank Schirrmeister, VP of solutions and business development at Arteris, to learn more about the Ncore Cache Coherent NoC IP.


Arteris Introduces NCore Cache Coherent NoC IP

Arteris says that Ncore significantly accelerates the design and implementation of system-on-chip (SoC) architectures, particularly for applications requiring high performance, scalability, and efficiency in data management.


“In the RISC-V world today, designs consist of hundreds of different blocks that need to interface with each other and with a wide variety of peripherals—whether that’s interfaces, memories, accelerators, or sensors,” Schirrmeister said. “Our NoC fits into this design flow by essentially figuring out how to connect the blocks best.”


Components of an Ncore Cache Coherent Interconnect

Components of an Ncore Cache Coherent Interconnect. 


Ncore facilitates coherent communication between various components within an SoC, including CPU cores, memory controllers, and input/output peripherals, by maintaining a consistent state of data across all caches. To do this, Ncore employs sophisticated mechanisms for cache coherency, such as directory-based and snoop-based protocols, which effectively manage data sharing and modifications across multiple cores.

These protocols are instrumental in minimizing data access latency and improving throughput, directly impacting the overall system performance. For instance, directory-based coherence scales efficiently with the number of cores, making Ncore useful for large-scale SoC designs.


Support for Processors, Protocols, and Protection

The IP stands out for its adaptability to various processor architectures, including Arm and RISC-V cores. It is even prevalidated with the latest Armv9 automotive cores. 

Arteris also built Ncore with multi-protocol support to allow designers to easily integrate IPs connected to the same NoC fabric. This support extends to fully coherent agent interfaces CHI-E, CHI-B, and ACE; ACE-Lite IO-coherent interfaces; and AXI for interfacing with devices without coherency needs. Ncore also lends flexible configuration options to SoC designers, whether they need to scale from heterogeneous to mesh topologies.

Ncore's processor compatibility, combined with its multi-protocol support, enables designers to integrate the IP into diverse SoC projects and applications, from consumer electronics to automotive systems.

Ncore's design is compliant with automotive industry standards such as ISO 26262. This compliance is crucial, with SoCs increasingly deployed in safety-critical applications, where failure can have dire consequences. 


Cache Coherency for Automotive

Cache coherency ensures all caches in a multi-processor system reflect the same view of memory. When one cache is updated, the changes are propagated across all caches, maintaining data consistency. This mechanism is essential in systems with multiple processors working on shared memory spaces. Data inconsistencies in these systems could lead to errors or unpredictable behavior. With cache coherency, any processor accessing a memory location will receive the most recent data, regardless of which processor last modified it.

“Cache coherency is all about sharing data between different units, like GPUs and CPUs,” Schirrmeister said. “Caches can talk to each other using our interconnect to figure out who has the latest cache entry.”


Automotive domains and their complexity

Automotive domains and their complexity

In automotive systems, cache coherency is necessary to support advanced driver-assistance systems (ADAS) and autonomous driving technologies, which demand high-performance computing with real-time processing capabilities. Modern automotive systems consist of many groupings of different functional blocks and processors, all of which are physically separated. Cache coherency must maintain data consistency across the multiple processing units within a car's SoCs to enhance the vehicle's decision-making speed and accuracy.


Improving Multi-Core Systems

Today's SoCs often require a mix of non-coherent and cache-coherent interconnects to optimize performance. Arteris provides two unique interconnect IP products to meet these needs: while the company's popular FlexNoC connects the NPU, CPU, video, PCIe, and safety subsystems, Ncore connects the CPU, GPU, memory, and safety island. The result of these products combined is better data flow and communication across the entire SoC. 

With Arteris' new Ncore Cache Coherent NoC IP, the company hopes to tackle some of the major challenges of tomorrow's computational demands. As industries become more reliant on multi-core systems and distributed processing, technologies like Ncore will play an increasingly important role in ensuring data availability and system coherence.

“If you find yourself having to connect many CPUs, memories, and peripherals, instead of learning all these standards or building things from scratch, you can essentially get the building blocks with Ncore,” Schirrmeister said. 



All images used courtesy of Arteris.