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At ISSCC, IMEC Unveils Charge-pump PLL Design for Short Range Radars

February 20, 2023 by Jeff Child

At this week’s 70th annual ISSCC event, research firm IMEC is presenting a phase-locked loop (PLL) IC design aimed at automotive and industry radar systems.

Today, the Belgium-based research and development organization IMEC unveiled the details of a novel phase-locked loop (PLL) IC design that they are presenting at this week’s 2023 International Solid-State Circuits Conference (ISSCC).

According to IMEC, the new device is a digitally calibrated charge-pump (CP) PLL aimed at generating high-quality frequency-modulated continuous-wave (FMCW) signals for mmWave radars. Applications include next-gen short-range automotive (in-cabin and out-of-cabin) and industrial systems—such as radars for collaborative robots (co-bots).

 

IMEC’s calibrated charge-pump (CP) PLL IC is designed for generating FMCW signals for mmWave radars.

IMEC’s calibrated charge-pump (CP) PLL IC is designed for generating FMCW signals for mmWave radars.

 

In this article, we examine the thinking behind IMEC’s PLL design, and we share insights from our interview with Jan Craninckx, IMEC Fellow.

 

Endless Appetite for Faster Radar "Chirp”

According to Craninckx, the heart of the FMCW radar is a frequency modulated sine wave. These kinds of radars transmit a sine wave whose frequency increases linearly in time. This sweep of a signal is referred to as “chirp” in radar parlance. 

Once the radar signal is reflected by the object, the signal is picked up by the receiver and mixed with the original chirp signal. From that information, the object’s distance and speed can be determined.

As Craninckx explains, the level of radar signal’s quality depends largely on the performance of the PLL used to generate the chirp signal. “A lot of the accuracy, range, noise—basically most any performance aspect of the radar—are determined by how clean of a linear frequency it can create, including the chirp,” says Craninckx.

With all that in mind, Craninckx says that IMEC’s novel PLL can produce highly linear, high-quality chirp signals centered around 16 GHz with a chirp bandwidth of 1.5 GHz. This level of performance, he says,is driven by markets, including automotive and industrial radars, where the appetite is just about endless for a fast, accurate, linear chirp

“They want performance that’s very linear, very fast, over a wide frequency range,” he says. “Also, the world is moving to multiple-antenna radars, so that means there's 15 receivers or more all using the same PLL sensor array.

 

“In order to put the right signal on all those receiving intermittent channels and have them all wait together—that definitely requires a chirp time that is fast.”

 

With IMEC’s PLL design, Craninckx says that a key achievement is getting chirp speeds down to 12 µs, but at a 41 kHz-rms error in frequency modulation (rms-FM-error). Moreover, the PLL enables ultra fast startup times—less than 1µs—along with low reset time between chirps of 1 µs.

 

Power-efficient Duty Cycles and CMOS Process

Clever management of the PLL’s chirp generation is also key to the power efficiency of the device. The PLL’s chirp generator operates in duty-cycled mode—synthesizing N chirps in one burst before powering down. This results in significant power savings because it makes good use of its time.

For example, the PLL consumes only 9.2 mW and 1.48 mW when operating in a 50 percent and one percent duty-cycled mode, respectively. Even after power-down mode, the rms-FM-error of the first chirp remains below 41 kHz, says Craninckx.
 

Built in 28 nm CMOS, shown here is the CP-PLL die with below 0.6mm2 active core area—PFD=phase-frequency detector; VCO=voltage-controlled oscillator; QDAC= charge-integrating digital-to-analog converter.

Built in 28 nm CMOS, shown here is the CP-PLL die with below 0.6mm2 active core area—PFD=phase-frequency detector; VCO=voltage-controlled oscillator; QDAC= charge-integrating digital-to-analog converter.

 

Critical to enabling this duty cycling performance was using a charge-pump (CP)-based PLL architecture. The device is fabricated in 28 nm CMOS technology, making it straightforward to manufacture. This CMOS technology is extended with a phase-offset compensation time-to-digital converter (POC-DTC) to facilitate fast self-calibration.

 

Suited for Short-range Radar

At ISSCC this week, IMEC is presenting a functional demo that integrates its CP-PLL with IMEC’’s existing 140GHz radar receiver and transmitter blocks. The demo is intended to show off the potential of the technology for future automotive and industrial applications.

On the automotive side, this includes short-range automotive radar applications ranging up to several tens of meters, such as in-cabin radar sensors to monitor presence, movements, and well-being of driver and passengers. It’s also well suited for out-of-cabin automotive sensors, such as parking assistance or vehicle detection, says IMEC.

 

Shown here is IMEC’s 140 MHz radar demo platform that it is presenting at this week’s ISSCC. It combines the novel PLL with IMEC's radar transmitter and receiver blocks.

Shown here is IMEC’s 140 MHz radar demo platform that it is presenting at this week’s ISSCC. It combines the novel PLL with IMEC's radar transmitter and receiver blocks.

 

According to IMEC, the PLL is also a fit for robotics radar applications. An example is cobot radar sensors. Such radars can enhance safety and efficiency of human-robot interaction in industrial environments.

Another use case is radar sensors mounted on small moving objects or vehicles such as drones. Importantly, the PLL could also be employed for up-conversion to mmWave radar signals with other carrier frequencies—80GHz for example.


 

All images used courtesy of IMEC