Can 3D NAND Flash Memory Side Step the Challenges of NAND?

August 18, 2021 by Ikimi .O

Traditional NAND often faces power, performance, and cost inefficiencies. NEO Semiconductor has announced recently-patented X-NAND to bypass these limitations.

Since NAND was commercialized and mass-produced in the early 1990s, developers have sought ways to increase performance while reducing cost per bit.

NEO Semiconductor—a company creating 3D NAND flash memory—was recently granted patents for a technology dubbed "X-NAND," which is purported to address some limitations of conventional NAND technology.


Limitations of NAND Technology

Existing NAND technology faces a number of obstacles, including: 

  • Full single-level cell (SLC) cache problems
  • Restricted number of planes
  • Inadequate page buffer architecture
  • High power consumption
  • Performance/cost inefficiency


Typical NAND flash cell

Typical NAND flash cell. Image used courtesy of Micron

The Full SLC Cache Problem

One of the reasons that NAND flash memory is usually associated with slower read and write speeds is its conventional SLC cache full problem. Although NAND's migration from single-level cell (SLC) to triple-level cell (TLC) and quad-level cell (QLC) significantly reduces the die cost and results in a 33 percent density increase, the increasing cell level adversely affects read and write performance. Consequently, this flash memory remains unreliable in high-performance applications like AI and 5G.


Cost and speed comparison between various memory cells

Cost and speed comparison between various memory cells. Image used courtesy of NEO Semiconductor


Restricted Number of Planes

To achieve greater read/write bandwidth and higher performance of flash memory architectures, manufacturers usually opt to increase the number of planes. This solution requires the bit line of each plane to be connected to page buffers, thus increasing the die size. 


Inadequate Page Buffer Architecture

The conventional NAND technology features an inadequate page buffer architecture. This technology requires a connection between the 16 KB page buffer and the corresponding 16 KB bit lines in each plane to perform read/write operations. The number of page buffers consequently limits its read/write size, leading to inefficiencies.


High Power Consumption

Power consumption in NAND technology is comparatively high due to its bit line capacitance. Thus, more power is needed for its operations. Its overall performance is also low and inefficient for its fabrication costs.


What Is X-NAND?

NEO Semiconductor intends to address these issues with its recently-patented 3D NAND architecture, also known as X-NAND. This technology is said to achieve the high performance of SLC flash with QLC densities. The company also claims that this innovation has a reduced footprint, optimized power consumption, and cooling capabilities at a reduced manufacturing cost.


X-NAND flash architecture

X-NAND flash architecture. Image used courtesy of NEO Semiconductor


The X-NAND architecture features several upgrades to the conventional NAND technology, with no significant change to its working principle. NEO Semiconductor asserts that NAND manufacturers can implement its technology using the existing NAND process.

Although X-NAND has a similar cell/array structure and technology to conventional NAND, this new architecture can support flash memory performance for machine learning, real-time analysis, cybersecurity, 5G, VR/AR, and several other applications.


SLC/QLC Parallel Programming

The X-NAND architecture addresses the SLC cache full problem with its novel SLC/QLC parallel programming, which allows the programming of data to QLC pages at SLC speed across the total memory capacity. As a result, this solution is well suited for data centers and NAS, which require heavy write systems.


Breakdown of 3D NAND

Breakdown of 3D NAND. Image used courtesy of NEO Semiconductor

16-Plane Architecture

Its 16-plane architecture allows for high parallelism at the chip level. Unlike conventional NAND, which is restricted to two to four planes for optimal functioning, the X-NAND chip can provide similar and even higher efficiency and parallelism with four to eight NAND chips. 

X-NAND architecture uses 2–16 planes, which drastically increases its performance up to 16 times while reducing its die cost by up to 33%. This flexibility allows manufacturers to optimize the architecture’s number of planes to meet customers’ performance and die cost requirements.

NEO Semiconductor observed the following X-NAND QLC architecture improvements over the conventional NAND QLC.




X-NAND vs. NAND QLC. Image used courtesy of NEO Semiconductor



NAND SLC and QLC Improvements

When compared with NAND SLC, the company observed the following improvement estimates for random read, random write, sequential read, and sequential write speeds. 



X-NAND vs. NAND SLC. Image used courtesy of NEO Semiconductor


The company achieved X-NAND QLC improvement over the NAND QLC by reducing its bit line capacitance, resulting in a corresponding reduction in the bit line RC delay. Its program verification time accounts for 90 percent of the program time, which causes the program speed to increase by three times.

Interestingly, increasing its number of planes to 16 resulted in higher read and write bandwidth, and opting for single-latch QLC read and multiple-plane QLC programs had significant positive effects on the sequential read and write speeds.


What Neo Semiconductor’s Patents Mean for Flash Memory

 NEO Semiconductor X-NAND comprises six distinct design solutions targeted at developing X-NAND architectures. This new technology is said to increase efficiency and cost-effectiveness for multiple bit lines read and write operations, including:

  1. Multiple BL write
  2. Multiple plane QLC program
  3. Program suspend read
  4. Multiple BL read
  5. Single latch QLC read
  6. SLC/QLC parallel program

NEO Semiconductor expresses optimism that its new IP may open doors to a wider range of innovative products.