Computing Startup NeoLogic Prolongs Moore’s Law With “Quasi-CMOS”
Working around deadends to Moore's law, NeoLogic uses single-transistor logic to significantly decrease transistor count in new VLSI designs.
For decades, Moore’s law has driven improvements in the semiconductor industry. Within the last 10 years, however, some industry leaders—including NVIDIA CEO Jensen Huang—believe that “Moore’s law is dead.”
Graph of the exponentially rising costs of advanced technology nodes. Image used courtesy of NeoLogic
Now, manufacturers and researchers are investigating new ways to scale semiconductors and improve performance. One startup, NeoLogic, is taking a unique approach to this challenge with a "new paradigm of VLSI design."
Challenges with Transistor Scaling
Moore’s law relies on manufacturing efforts to drive the transistor gate length down by a factor of 0.7x every generation. Decreasing transistor gate length produces many important benefits: it decreases the cost of circuits, lowers power consumption, improves performance, and boosts transistor count.
However, as scaling has continued into the 5nm realm and below, scaling may create more problems than its solves.
CMOS performance, power density, and circuit density trends. Image used courtesy of NASA
One of these problems is circuit complexity. As more transistors are added to the same area chip, designs become clustered and complex, requiring elaborate delivery schemes for power, clock, and global and local signals. Eventually, this complexity is a limiting factor in how small transistors can be scaled and how much performance can be achieved at scale.
Another challenge is power density. With more transistors in a smaller area, the amount of power being consumed per area increases significantly. This leads to design reliability issues because of high circuit thermals.
NeoLogic Devises a "Quasi-CMOS" Solution
To address these challenges, startup NeoLogic has devised a unique solution.
While NeoLogic has not revealed many details about its NeoMOS IP, the company has explained that the Quasi-CMOS architecture integrates single-transistor logic (i.e., nMOS or pMOS) together with CMOS logic to create logic gates and circuits. According to the company, adding single-transistor logic significantly decreases transistor count in VLSI designs.
NeoLogic’s claimed benefits of NeoMOS. Image used courtesy of NeoLogic
The benefits of NeoMOS include decreased cost, area, power consumption, and design complexity, NeoLogic claims. Compared to standard CMOS offerings, NeoMOS is said to reduce power consumption by 50% and reduce the area by 40% while maintaining or improving circuit latency. NeoLogic says this amounts to a 3x improvement in performance-per-watt and allows companies to effectively leapfrog three node generations.
As it currently stands, NeoLogic sells its IP blocks through licensing agreements, but one day the company hopes to sell its own processors and other technology based on its NeoMOS technology.