Developers Turn to 5nm ASICs to Meet 5G Data Center Loads

December 02, 2020 by Luke James

2020 has seen a swathe of progress on the 5nm process node led by TSMC. Here’s a quick look at recent developments involving 5nm ASICs.

According to recent market research carried out by MarketsandMarkets Research, the 5G chipset market is expected to grow from $12.8 billion in 2020 to more than $67 billion in 2027, representing a compound annual growth rate of 26.7 percent. 

The report identifies the major drivers for this growth as the increasing demand for high-speed Internet, better cellular IoT connections, and an increase in mobile data traffic. Accordingly, it predicts that 10nm to 28nm will account for the largest share of the 5G chipset market during the forecast period.


Sampling of Qualcomm's 5G chipsets

Sampling of Qualcomm's 5G chipsets. Image used courtesy of Qualcomm

However, some of the major process nodes on which 5G chipset components are manufactured include 5nm and 7nm, and it’s the former that many fabs have recently been experimenting with. 

Here’s a look at how three industry stalwarts—Taiwan Semiconductor Manufacturing Co. (TSMC), Marvell, and Broadcom—are making progress with 5nm ASICs.


Taiwan Semiconductor Manufacturing Co.

TSMC was the first chip manufacturer to deliver a complete design infrastructure for 5nm process technology back in early 2019. 

At the end of December, the company announced that it would be making 5nm ASICs for a select few customers. It would divvy out of 5nm products to Bitmain and schedule volume production in the first half of 2020.

TSMC says that its 5nm node brings with it huge improvements in power, performance, and area, in addition to a 1.84x logic density increase, when compared with its 7nm process, which itself is still new. 


Timeline of TSMC's foundry process technology

Timeline of TSMC's foundry process technology. Image used courtesy of TSMC

Then, in August of this year, TSMC announced its first seven customers for 5nm production: Advanced Micro Devices, Apple, Bitmain, Intel (plus Altera), MediaTek, NVIDIA, and Qualcomm. This was followed in October by Apple’s new iPhone 12 line-up, which uses the Apple A14 Bionic 64-bit Arm-based SoC, one of the first devices to be commercialized on TSMC’s 5nm process node

Looking ahead, TSMC has plans to commercialize the 3nm node in the near future.



More recently, in mid-November, Marvell unveiled the industry’s first 112G 5nm DSP-based SerDes built on TSMC’s 5nm process node

According to the announcement, the SerDes features industry-leading performance, power, and area, “helping to propel 112G as the interconnect of choice for next-generation 5G, enterprise, and cloud data center infrastructure.” Marvell acquired its ASIC division just over four months ago in July.


Benefits of Marvell's 5nm technology in data center

Benefits of Marvell's 5nm technology in data center network switching silicon. Image used courtesy of Marvell

Marvell calls its 5nm technology portfolio the “most advanced” in the industry.

The 112G 5nm SerDes product forms part of Marvell’s IP portfolio that addresses the full spectrum of infrastructure requirements. It includes processor subsystems, SoC fabrics, chip-to-chip interconnects, and a range of physical layer interfaces. It’s capable of operating across channels with greater than 40dB insertion loss, providing a margin that’s critical for high-reliability infrastructure applications while reducing power consumption by more than 25 percent compared to 7nm. 

Marvell’s ASIC customers will benefit from these gains in power, performance, and area metrics by being able to better scale to meet growing interconnect requirements, said Sandeep Bharathi, Marvell’s SVP of central engineering in the announcement.



Broadcom has just announced the sampling of its 5nm ASIC device for data center and cloud infrastructures. Also built on TSMC’s 5nm process node, the device incorporates PCIe Gen5 protocol, 112-Gbps SerDes, HBM2e memory operating at 3.6 Gbps, and 3.6-Tbps Die2Die PHY IP utilizing TSMC CoWoS interposer technology.

The company says that it has several ASICs on the 5nm process node in the development pipeline that will target artificial intelligence (AI), high-performance computing, and 5G wireless infrastructure applications with two times the performance for training and inference applications.  


Broadcom's new 5nm ASIC joins a host of other IP geared for the data center

Broadcom's new 5nm ASIC joins a host of other IP geared for the data center. Image used courtesy of Broadcom

“Broadcom’s pioneering ASIC leverages both N5, the industry’s most advanced silicon technology, and our high-performance CoWoS integration solution to address the demanding requirements of next-generation cloud and data center applications,” said Kevin Zhang, SVP of business development at TSMC.