Higher Memory, Compute, and Security: Xilinx’s Versal HBM Platform Speeds Past DDR5

July 14, 2021 by Adrian Gibbons

Fast on the heels of the AI Edge series, Xilinx releases the Versal HBM Advanced Compute Acceleration Platform (ACAP), claiming 800% more memory bandwidth at 63% lower power over DDR5.

Today, Xilinx is announcing its Versal HBM series, an expansion of the Versal Advanced Compute Acceleration Platform, which claims to addresses three growing challenges in data traffic and security.

These challenges are: 

  1. Memory bandwidth bottlenecks concerning network traffic, 
  2. An exponential growth pattern for network traffic, and 
  3. A growing subset of data requiring security present a trifecta of industry pain points.


The Versal HBM chip

The Versal HBM chip. Image used courtesy of Xilinx


Our team at All About Circuits recently sat down with Mike Thompson, Senior Product Line Manager for the Versal Premium and HBM ACAPs, to discuss how Xilinx is leveraging design expertise to bring the Versal HBM to market.


Building a Versal ACAP Product Family

Engineers may be curious about how the development team at Xilinx can push out new silicon designs for the Versal HBM, considering that Xilinx announced the Versal AI Edge series only a month ago.

All About Circuits was curious as well, so we asked Mike for a 'peak behind the curtain.' According to Mike, the platform is exceptionally modular, allowing for blocks of IP interchanges. 

Specifically, he likened it to Lego blocks, that the Versal platform is "almost like a Lego block where you have some big squares, a Lego foundation, and we can fairly readily support functions or pop up blocks and drop in new blocks in a very modular fashion."


Building a product solution from proven IP makes Versal more agile

Building a product solution from proven IP makes Versal more agile. Screenshot used courtesy of Xilinx


Using 4th generation Stacked Silicon Interconnect (SSI) technology, Xilinx has been able to remove one of three super logic regions (SLRs) from a Versal Premium and replace it with the high bandwidth memory (HBM) module required for the new series.

Thus, Xilinx can build an ACAP to suit industry needs; however, what specific benefits does the Versal HBM offer to the industry that necessitated its development? 


Overcoming Performance Bottlenecks With the Versal HBM

The Versal HBM ACAP sits at the intersection of three technologies enabled by ultra-high performance heterogeneous integration. The adaptable compute engine, which is the cultural heritage of Xilinx at work, is combined with fast memory and secure connectivity.

Based upon the 7 nm TSMC FinFET node size, the Versal HBM is said to incorporate the functionality of up to 14 FPGA cores with 32 DDR5-6400 chips. 


The intersection of the Versal HBM platform. Image used courtesy of Xilinx


Below this article will delve into these three key technologies, all of which work together to bring the Versal HBM to life. 


High Bandwidth Memory Reduces Latency

Latency is the performance killer in high-throughput applications. The Versal HBM ACAP claims to address latency with an onboard memory transfer rate of 820 GB/s, compared to 102 GB/s with four external DDR5-6400 chips.

Moving that much data around a system-on-chip (SoC) requires dedicated protocols and hardware; this is where the network-on-chip (NoC) mesh comes into play. By interlinking the fabric for the three compute engines, along with the hardened I/O, the system NoC can support up to 2.2 Tb/s of throughput. 


Flexible architecture for extreme data movement.

Flexible architecture for extreme data movement. Screenshot courtesy of Xilinx


Improving throughput solves one issue; however, unsecured data is a growing concern among industry hyper-scalers. The amount of data that does not require security is dwindling. Meanwhile, the ratio to secure vs. unsecured data seems to be going in the wrong direction


Addressing Growing Rates of Data Insecurity

The Versal HBM claims to have the worlds' only 400 G hardened crypto engine on an adaptable platform to help address these security concerns. The platform supports up to 1.2 Tb/s of in-line bulk encryption for AES-GCM-256/128, MACsec, and IPsec. The flexibility of the ACAP also allows for various SerDes line rates from 10 G up to 100 G. 

Compared with industry competition, the platform is a capable next-generation firewall with 250% increased session capacity with 38% less power consumption in an 89% reduced design area. 

Lower latency and real-time security lead directly into the final prominent feature of the Versal HBM–––accelerating larger data sets.


Accelerating Larger Data Sets With Adaptable Compute

Like recommendation engines and fraud detection, twelve major applications make up the bulk of the current hyper-scale deployments. The Versal HBM is said to handle a 4x increase in database size, along with a 200x faster run-time for recommendation engine performance. 


Twelve key applications primed for acceleration.

Twelve key applications primed for acceleration. Screenshot used courtesy of Xilinx


The Versal platform, including the new HBM series, appears to offer some of the highest levels of integration for an SoC in the industry. The result is significant performance gains for the most demanding applications, with better power efficiency derived from the integration of hardened I/O and HBM modules. 

Xilinx notes that this level of integration is not needed for all applications. The Xilinx UltraScale+ FPGA platform can offer significant benefits for designs requiring more mid-range performance (compared to Versal) or a more flexible platform.



What are your thoughts on the Xilinx ACAP product class? Which element of the architecture strikes you as most applicable to your engineering projects? Let us know in the comments below.