A Need-to-Know on Micron’s Hybrid Memory Cube Technology
Micron's HMC started shipping in September. Here's a rundown on key features of the very welcome memory solution.
With the increasing demand of high memory bandwidth in fields like Digital Signal Processing and ASIC Prototyping, a memory solution with a high bandwidth data gateway could be the answer we've been waiting for.
The Hybrid Memory Cube (HMC) is the most recently developed memory device, featuring an entirely new category of high performance memory and delivering unprecendented system performance and bandwidth. Micron’s HMC design combines advanced logic and DRAM layers into one optimized 3D package that leverages through-silicon via (TSV) technology. The high density nature of the HMC will enable next-generation networking. The HMC will also be instrumental in reducing the power consumption in supercomputing and data centers.
The problem of latency in memory devices, also known as the classic “memory wall,” was always seen as an insurmountable problem. Over time, the bandwidth of current DRAM modules has bottlenecked system performance in the world of high performance computing. HMC is the long-awaited solution to these conventional memory problems. The high performance levels of the HMC have been instrumental in breaking the memory wall, delivering very high bandwidth and introducing an energy efficient memory system.
Theory of Operation
The HMC is built by creating a stack of heterogeneous die. Various application-specific logic is combined with a standard DRAM building block. Each of the 1 GB DRAM layers used in the stack is optimized for concurrency and high bandwidth. Memory is organized into functionally and operationally independent vaults. Each vault contains its own memory controller, also called the vault controller. The vault controller is responsible for managing all memory reference operations within that vault.
Stack of heterogeneous die
The device uses fine pitch copper pillar interconnects. The logic die uses several high-performance transistors for DRAM sequencing, refresh, data routing, error correction and high-speed interconnects to the host. The use of TSVs empowers thousands of connections in the vertical direction (Z- direction).
Diagram showing fine pitch copper interconnect
Due to TSV’s short interconnect length, high interconnect density, and small footprint, it is an essential element for both wafer-level 3D integration and packaging-based 3D integration. Use of TSV enables lower latency, lower power, and superior electrical performances.
Diagram showing different layers and TSV connections
The use of through-silicon vias greatly reduces the distance data needs to travel, which results in improved power. It's been tested that an HMC device uses 70% less energy per bit than existing memories like DDR2 and DDR3. In HMC technology, the host memory controller no longer needs to perform refresh operations, as it's controlled by the vault controller.
The Micron Hybrid Memory Cube has several key benefits over using the DDR3 module: the HMC provides up to 15 times the bandwidth of the DDR3 module and it consumes up to 70% less power per bit rather than the existing memory. The HMC technology has had phenomenol success in reducing the memory footprint. It takes 90% less space compared to other RDIMMs currently in use. Since it has logic layer flexibility, it can be tailored to multiple platforms, which increases the scope of applications of HMCs. HMCs massive parallelism has proved instrumental in decreasing the system latency. Its RAS features enable embedded error checking and correction capabilities, which makes the HMC a more resilient memory system compared to DDR3 modules.
Here's a direct comparison of HMCs and DRAM based on memory interaction:
|No.||Dynamic Random Access Memory (DRAM)||Hybrid Memory Cube (HMC)|
|1||Multi-core CPU direct connection to DRAM-specific buses||Direct connect to HMC logic chip via abstracted high-speed interface|
|2||Complex scheduler, deep queues, high reordering especially writes||No need for complex scheduler, just thin arbiter, shallow queues|
|3||Result is conservative, evolutionary, uncreative, slow performance growth||Logic layer flexibility allows HMC cubes to be designed for multiple platforms and applications without changing the high-volume DRAM.|
Technology comparison of 1st generation HMCs with available DDR modules
Micron started shipping HMCs at the end of September, 2014. Some of the major developing members as well as customers of the Micron’s HMC are Altera, ARM, IBM, Open-Silicon Inc., Samsung Electronics Co., Semtech, SK Hynix and Xilinx. Along with these eight industry leaders, there are over 150 additional organizations pursuing adopter status. Micron has not yet disclosed the price, but it claims that the Hybrid Memory Cube’s increased density per bit and the decreased form factor lowers the total cost of ownership by allowing more memory into each computer and using 90% less space compared to currently used RDIMMs in the industry. It's too soon to tell if this will actually be a needed seachange, but early outlooks seem promising.