Keysight Rolls Out Two New Test Solutions at DesignCon 2022
Addressing the challenges of 1.6 Tb/s pathway test and PCIe 6.0 validation, Keysight is releasing two new test products at this week’s DesignCon 2022.
The annual DesignCon conference is a key event aimed at engineers involved in all manner of high-speed designs—everything from high-speed networking to speedy serial bus technologies. With that in mind, it is no surprise that test instrumentation vendors are well represented at the show.
Along just those lines, Keysight Technologies released two test solutions at this week’s DesignCon 2022:
- The first is the M8050A, a 120 gigabaud (GBd) tester for BERT (Bit Error Ratio Test) that supports 1.6 Tb/s (trillion bit per second) pathways.
- The second is a new end-to-end validation solution to help engineers transition from the 5.0 version to the 6.0 version of the PCI Express (PCIe) serial bus.
Keysight's M8050A helps engineers test bit error ratio, as shown. Image used courtesy of FOSCO
Recently, All About Circuits spoke to Keysight representatives to get perspective on these new products.
In this article, we provide an overview of the new products and share insights from Keysight on what problems the products solve for system designers.
BERT Tester Supports 1.6 Tb/s
According to Keysight, the M8050A tester was designed to enable engineers to design, characterize, and do serial testing on I/O ports of ICs, transceiver modules, sub-components, boards, and systems at rates ranging from 2 GBd to 120 GBd.
Such testing is required in a variety of applications, including:
- Data centers
- Communication systems
When dealing with high transmission speeds, data loss, and distortions are a challenge. Addressing those needs, the M8050A claims to provide high signal integrity resulting in more test margin. The tester supports non-return-to-zero (NRZ), pulse amplitude modulation–4 (PAM4), PAM6, and PAM8 line coding, which are important at 1.6 Tb/s speeds. Additionally, there is a built-in seven-tap de-emphasis in order to improve channel loss compensation.
The new M8050A 120 GBd BERT tester (left) and Infiniium UXR Series oscilloscope (right). Image used courtesy of Keysight
As shown in the image above, Keysight’s Infiniium UXR Series oscilloscope is extended to act in combination with the M8070B BERT system software as an acquisition-based error analyzer. This forms a complete receiver test system to evaluate bit error ratio up to 120 GBd.
During our interview, we asked Oliver Funke, Product Manager for Keysight’s BERT tester, what kinds of chips need this type of testing system at these kinds of speeds.
According to Funke, every two years application-specific ICs (ASICs) double in switch routing capacity. In a typical scenario, data must be transferred from optical transceivers at the server board front panels, to the switch routing ASIC, and then to the backplane of the server.
“Each of these ASICs have interfaces to manage communication with other ASICs on the server board. As the transmission speed increases, the channel impairments between these devices significantly increase, making the move to higher speeds challenging. Test instruments are required to have the best signal integrity, with enough test margin to evaluate the real performance of the device under test (DUT), all the while not being limited by the test instrument.”
Despite how ahead of the game Keysight tries to be, there are certain fundamental challenges inherent in test and measurement and those hurdles require planning ahead.
Challenge to Keep Pace
Designing test gear is challenging because you must use technologies that are as fast or faster than the chips you are testing. That’s true of oscilloscopes and logic analyzers, and testers like the M8050A as well. That means planning years ahead.
To make that happen, Funke says Keysight is active in many wireline standards groups and that gives Keysight engineers early insights into upcoming developments.
The company can then start early technology developments. Even when product details of new high-speed chips are limited, the core requirements are usually quite clear. This consistent aspect enables Keysight to plan the right instrument products available for engineer’s demands. That’s typically two years ahead of broad technological deployments, says Funke.
Pre-planning helps instrumentation vendors like Keysight keep up with new technologies, but the throughput demands are always trending upwards.
AI is Raising Throughput Demands
The speeds supported by test products like the M8050A are significant these days because of the sheer level of data throughput happening in many applications. Keysight lists examples such as fully automated dark factories and closed-loop digital twins for the metaverse. Such applications and services can churn out huge amounts of artificial intelligence (AI) workloads.
We asked Funke what the impact of AI workloads is in the context of data centers in particular.
“AI is the core driver of higher throughput requirements within the data center. That’s because AI requires fast and more power-efficient links between high-performance computing resources distributed in a computing cluster (in a data center). AI manages a huge amount of data, which is evaluated to deliver the desired results.”
That AI-driven throughput has to be matched with data center ASICs and server boards that can keep up, and testers like the M8050A could help engineers design and test those technologies.
The high-speed server technologies needed for today’s advanced data centers really push the limits on today’s test gear. That same theme applies to Keysight’s second DesignCon 2022 new product, this time focusing on PCIe.
Test Gear for PCIe 5.0 to 6.0 Transition
Keysight’s second product release at this week’s DesignCon is an end-to-end PCIe test solution aimed at smoothing the transition for engineers as they migrate their designs from PCIe 5.0 to PCI 6.0. The solution is designed to enable simulation, pathfinding, characterization, validation, and compliance testing of PCIe designs says the company.
Keysight mentions how PCIe 6.0 presents new challenges not seen before with the PCIe bus. One challenge comes in the form of eye pattern heights. PCIe 6.0 moves from NRZ to PAM4, with eye pattern heights of only 6 mV, compared to 15 mV in PCIe 5.0. Measuring eye pattern heights as small as 6 mV requires better noise performance in instrumentation.
The P5552A PCIe Gen5 analyzer and P5551A PCIe Gen5 exerciser are parts of Keysight’s end-to-end PCIe validation offering for PCIe 5.0 and 6.0. Image used courtesy of Keysight
As with the M8050A discussed earlier, here again, AI workloads are a factor in the throughput demands of data centers and edge computing devices. Those demands are driving a transition from PCIe 5.0 to 6.0 in many cases. The pressure is on new PCIe devices to keep pace with Ethernet network interfaces in data centers.
Also, a factor is the CXL standard (compute express link) that is gaining steam. Built on PCIe’s physical and electrical interface, the open standard CXL standard is a CPU-to-device and CPU-to-memory interconnect standard aimed at data center computers.
End-to-End PCIe Validation
Keysight currently offers a portfolio of physical-layer test products that are approved by the PCIe’s standards organization, the Peripheral Component Interconnect Special Interest Group (PCI-SIG). This portfolio includes gear for testing transmitters and receivers for all generations of the PCIe specification and those products are supported by the PCI-SIG integrators list.
This new release extends that portfolio to cover PCIe protocol, making it what it claims is the first end-to-end solution from simulation to full stack validation.
The new PCIe test solution taps Keysight’s physical layer-system simulation, physical layer interconnect, transmitter (Tx), and receiver (Rx) test.
Now, at DesignCon this week, the company is showing for the first time a new PCIe protocol layer test solution consisting of hardware and software products. This addition results in interoperability and support across the entire design cycle from a single vendor, says the company.
Engineers can do end-to-end verification of chips and sub-systems using common software platforms and built-in test automation capabilities.
The Race Never Ends
Clearly chip interfaces, bus protocols, and networks continue to get faster with each new generation of technology. New instrumentation gear like these new products, and others showcased at DesignCon 2022, can help fill a critical need as data throughputs, driven by AI workloads and other factors, that make testing and validation more challenging.