Microchip Faces Connectivity Issues for PAM4 with “Most Compact” Ethernet PHY

September 09, 2021 by Jake Hertz

The demand for better connectivity has prompted the shift to 112G PAM4, though there are many challenges like signal integrity. Taking on these challenges, Microchip unveils its latest solution.

The advent of modern-day technologies, including 5G, cloud services, and machine learning (ML), along with the general growth of the internet, has created a significant increase in data center traffic. 

To deliver the higher bandwidth required, the industry has started to shift away from traditional non-return-to-zero (NRZ) schemes in search of something better. 

One scheme that has gained a lot of traction recently is PAM4; however, its integration has been hindered by many challenges. A possible solution hoping to address some of these issues comes from Microchip by announcing its newest product: a new 1.6T low-power Ethernet PHY (physical layer). 


Microchip's "industry's most compact" 1.6T Ethernet PHY solution. Image used courtesy of Microchip


This article will discuss the industry move to PAM4, what those challenges are, and how Microchip's new offering could pave the way to better and faster connectivity. 


Understanding PAM4 

To begin with, PAM4 is short for 4-level pulse-amplitude modulation and is a communication scheme that has recently found large adoption levels in data communications. 

As the name implies, the concept of pulse-amplitude modulation is that the transmitted data is encoded in the amplitude of transmitted pulses. 

While this scheme may sound a little confusing, it is actually the standard scheme of binary digital communication, where high logical levels represent one and low logical levels represent zero. This scheme is formally known as PAM2 or non-return-to-zero (NRZ). 


NRZ vs PAM4 signaling.

NRZ vs PAM4 signaling. Image used courtesy of Fiber Mall


As for PAM4, the concept is the same, but instead of two discrete amplitudes, the data is communicated via four discrete amplitudes. 

This increase means that each symbol period can represent 2 bits of logic (0, 1, 2, 3) instead of just one. The result is that PAM4 can transmit twice as much data per symbol period, making it a potential solution to the higher bandwidth needs of today's data centers. However, despite the benefits PAM4 creates, there are still many challenges to it, especially concerning signal integrity (SI).


Challenges with Signal Integrity 

Unfortunately, PAM4 is also plagued with several design challenges

With four discrete voltage levels, PAM4 offers increased signal complexity with 12 distinct symbol transitions, three eye diagrams per bit period, and SNR degraded by at least 9 dB. 

It also comes with a broader power spectrum than PAM2, with more power concentrated at higher frequencies, which, coupled with a relatively low Nyquist frequency, results in signal integrity issues for PAM4, including crosstalk and capacitive coupling. 


PAM4 eye diagram showing eye compression.

PAM4 eye diagram showing eye compression. Screenshot used courtesy of Keysight Technologies


PAM4 also introduces novel nonlinearities such as "eye compression," when there are variations in the eye heights of the three eye openings, and "timing skew," when the centers of the three eyes are misaligned. All of this comes on top of the preexisting communication issues like clock skew, jitter, and noise. 

Since PAM4 has the potential to be beneficial but has so many challenges, companies are working to find ways around them. As mentioned, one recent solution comes from Microchip. 


Pushing Connectivity to the Future with Microchip

To help overcome the challenges with PAM4, Microchip announced its newest product yesterday: a new 1.6T low-power Ethernet PHY. 

This new device, the PM6200 META-DX2L, claims to be the industry's most compact solution, coming in at a 23 mm × 30 mm package. The solution integrates a 112G PAM4 SerDes technology and supports Ethernet rates from 1 to 800 GbE. Also, Microchip claims this solution offers 35% less power per port than its 56G PAM4 predecessor, META-DX1

All in all, this company believes that designers will use this new solution to support infrastructure interface rate for: cloud data centers, AI/ML compute clusters, 5G, and telecom service provider infrastructure, either via long-reach direct attach copper cables, backplanes, or connections to pluggable optics. 

Overall, the new solution from Microchip proposes to help alleviate some of the design and SI issues involved in designing PAM4 electronics. 

Altogether, Microchip is hot on this product, saying that it can deliver up to 1.6T of bandwidth within a low-power architecture and in a small footprint. With those things in mind, it claims that the META-DX2L PHY can double the bandwidth versus other solutions on the market, all while trying to establish a new level of power efficiency.

Though this is just one recent solution, it could be a step in the right direction for pushing forward the future of connectivity.