Micron Takes 3D NAND to Towering New Heights— 176 Layers to Be Exact

November 17, 2020 by Luke James

In what the company has described as a breakthrough in flash memory, performance, and density, Micron has shipped the world’s first 176-layer 3D NAND.

In a recent announcement, Micron, which ranks sixth in the global NAND flash industry, unveiled what it terms "the world’s first 176-layer NAND product" well ahead of Samsung Electronics, the industry’s current top dog. According to Micron, the new technology and its advanced architecture represent a “radical breakthrough" for storage applications.

“Micron’s 176-layer NAND sets a new bar for the industry, with a layer count that is almost 40% higher than our nearest competitor’s,” said Scott DeBoer, executive VP of technology and products at Micron.


A Novel Replacement-Gate Architecture

As Moore’s Law slows down, innovations like the 176-layer NAND device are important to help the industry keep up with growing data requirements. The technology is almost 10 times denser than early 3D NAND devices, which means devices like smartphones can do and store more while becoming more affordable. It’s also great news for widely-used applications like cloud storage, which are incredibly data heavy. 

Not only is the device denser but it also incorporates the "industry’s highest data transfer rate" of 1,600 megatransfers per second (MT/s) on the Open NAND Flash Interface (ONFI) bus. According to Micron, this feature is made possible through innovative circuit design and architectural changes.


CMOS under array

Micron’s novel CMOS-under-array technique builds the multi-layered cell stack over the chip’s circuitry, allowing more memory to be squeezed into a tighter space while decreasing die size. Image used courtesy of Micron


Here, Micron has replaced floating-gate with a charge-trap approach (PDF), combining it with its novel CMOS-under-array architecture. This structure opens doors for improved performance and density, according to the company. This fabrication technique also allowed Micron to fit all 176 layers into the same height; it could previously only fit 64. 


The capacitive structure of a traditional gate NAND and a replacement-gate NAND

The capacitive structure of a traditional gate NAND and a replacement-gate NAND. Image used courtesy of Micron (PDF)

The 176-layer NAND creates a cell-to-cell approach that Micron says is closer to an interaction-free structure, using a non-conductive layer of silicon nitride that acts as a NAND storage cell and traps electrical charges. This layer then surrounds the inside of the control gate of the cell to act as an insulator.


30 Percent Smaller and 35 Percent Faster

The device is Micron’s fifth generation of 3D NAND and second-generation replacement-gate architecture technology. According to Micron, it’s the most technologically-advanced NAND node on the market since layer count correlates directly with technological power.

Compared with previous generations of Micron 3D NAND, Micron says its 176-layer NAND improves both read and write latency by more than 35 percent, massively increasing application performance. It’s also described as having a 30 percent smaller die size than what’s currently available on the market. 


Micron’s 176-layer achievement

Micron’s 176-layer achievement puts the company ahead of competitors like Samsung and SK Hynix. Image use courtesy of Micron


With its 176-layer NAND device, Micron intends to serve a range of storage applications including mobile storage, vehicle infotainment, data center solid-state drives (SSDs), and autonomous systems. For data center SSD applications, the device features improved quality of service, which is an important inclusion for data center SSDs and other data-intensive environments and workloads. 

“We are deploying this technology across our broad product portfolio to bring value everywhere NAND is used, targeting growth opportunities in 5G, AI, cloud and the intelligent edge,” said Sumit Sadana, executive VP and chief business officer at Micron. The company currently has a large share of the automotive memory market.


A Potential Boon for Competition

While competition in this space has somewhat slowed down over time, Micron’s announcement could inspire more competition and innovation in cell-stacking technology.

Once upon a time, cells were arranged in a single layer. Then along came Samsung with a 24-layer 3D NAND flash in 2013. Vertical stacking soon became the semiconductor industry standard as the benefits of it—namely fewer interferences between cells—were realized. 


The physical differences between current NAND and replacement-gate NAND

The physical differences between current NAND and replacement-gate NAND; "higher tier stacks mean more storage capacity," Micron explains. Image used courtesy of Micron (PDF) 

The last major NAND achievement in terms of layer volume was that of SK Hynix in June 2019 when its 128-layer 4D NAND flash was announced. Samsung is already planning to mass-produce 7th generation V-NAND flashes with 176 layers by Q3 2021, and SK Hynix is planning a 176-layer 4D NAND flash during the first half of 2021. 

Micron’s achievement puts them well ahead in terms of technology. Currently, most firms are still wrangling with 128-layer 3D NAND, which Micron began producing in April this year.