Peaking at 232 Layers, the Sky’s the Limit for Micron’s 3D NAND
The vertically-layered memory technology from Micron marks the industry’s highest areal-density NAND chip.
With the proliferation of 5G and cloud computing has come an enormous boom of data and traffic. This increased dependence on data has made the industry equally dependent on storage and memory technologies.
However, like other areas in the semiconductor industry, the memory industry is currently in need of new architectures to help push the technology forward. This week, Micron made headlines in the memory industry when it announced the production of its 232-layer 3D NAND technology.
232-layer NAND flash. Image used courtesy of Micron
Why 3D NAND Anyway?
Today, NAND flash technology is pushed to new limits in terms of power efficiency, throughput performance, and monolithic die capacity. Because of these unprecedented requirements, traditional 2D NAND flash technologies have quickly become obsolete.
One challenge with traditional NAND technology is that the physical distance between cells on a single transistor plane decreases as cell size decreases. The challenge here is that flash memory works by storing voltage states within a single transistor cell, and as the distance between cells decreases, current leakages on the transistors also increases. For this reason, NAND flash manufacturers have been limited in traditional scaling, unable to go much lower than 13nm without sacrificing performance.
The architecture of a 3D NAND solution. Image used courtesy of Enterprise Storage Solutions
Instead, many have turned to 3D NAND technology to continually improve NAND flash. 3D NAND refers to a NAND architecture in which NAND cells are stacked vertically into layers on top of each other instead of side by side in conventional NAND. In Micron’s 3D NAND technology, flash storage chips are composed of storage cells divided into blocks and planes, where the cells each have word lines connected to them for read/write access.
There are several advantages to a move to a 3D architecture. The most notable is the ability to space out transistor cells from one another to avoid leakages and interference from adjacent cells. In this way, 3D NAND allows designers to increase memory density without sacrificing performance—side-stepping the performance limitations of continual scaling in the process.
Micron Stacks a 232-layer NAND
This week, Micron announced the volume production of its 232-layer 3D NAND technology.
A follow-up to the company’s previous 176-layer generation, the 232-layer 3D NAND technology builds off of Micron’s CMOS under array (CuA) architecture. In this architecture, Micron stacks the bit cell array of the NAND into layers to provide the most amount of bits per square millimeter of silicon possible. In doing this, Micron aims to achieve the lowest cost per bit and the greatest density possible.
Current NAND capacitive structure vs. Micron's 3D RG NAND flash storage. Image used courtesy of Micron
Thanks to the high layer count, the new 232-layer NAND flash technology can deliver up to one terabit per chip in an 11.5 mm x 13.5 mm package. Compared to Micron’s previous 176-layer technology, the 232-layer solution represents a 45% increase in bit density per area in a 28% smaller package.
Beyond density, Micron claims advances in performance as well. According to Micron, the new 232-layer NAND device offers the industry’s highest layer count, the highest areal density (bits/mm2), and the fastest I/O speed at 2.4 GB/s. Compared to Micron’s previous 176-layer NAND offerings, the 232-layer, 6-plane architecture is said to enable 100% higher write bandwidth, 75% higher read bandwidth, and a 50% increase in transfer rate. Micron believes these improvements per die will translate into greater performance and energy gains in future embedded NAND solutions.