Microsemi Releases Libero SoC 12.0, a New Unified Design Suite for SoC FPGA Development

January 31, 2019 by Robin Mitchell

This week, Microsemi announced their latest unified design suite to help streamline the process of developing on FPGAs.

This week, Microsemi announced their latest unified design suite to help streamline the process of developing on FPGAs.

FPGAs are becoming an increasingly critical component in modern electronics due to their re-programmability and flexibility. But, for many engineers, they remain a complex and daunting form of hardware to design with. Microsemi aims to address these difficulties with the release of a new design suite for their FPGA solutions.


The SmartFusion2 Advanced Development Kit uses an SoC FPGA courtesy of Microsemi.


Let's take a look at how FPGAs have risen to prominence and why the new Microsemi design suite is of note for designers.

FPGAs: Increasing Complexity and the Need for Customization

Before the era of FPGAs and CPLDs, designers used glue logic and ASICs (application-specific integrated circuits) to accomplish specific design tasks. While glue logic easily allowed the creation of customized logic circuits, ASICs provided a method for engineers to combine all their glue logic into a single IC package. While this was useful for miniaturization, it was not practical for low-volume products as ASICs are essentially customized silicon devices at the metal interconnection level. Designing them is a very expensive process.

One option for creating custom logic tables is with the use of a parallel EEPROM whose address inputs can be used as logic inputs and the 8-bit data output bus as 8 possible logic outputs. However, this method has some issues, including the inability to implement feedback and edge-sensitive inputs.

These issues resulted in the industry creating PLAs (programmable logic arrays) and CPLDs (complex programmable logic devices). PLAs and CPLDs allow a designer to create custom logic circuits using a single IC and often integrate feedback and flip-flops. While these devices (such as the XC9536 from Xilinx) have a limited number of logic units and are not always a replacement for ASICs, they have proven to be invaluable to the industry.

As time has progressed and technology has improved, however, the CPLD has quickly been replaced by FPGAs and the number of features integrated onto these devices has exploded. FPGAs can now include many features including processors, memory, I/O peripherals, protocol controllers, security, and even as many as 500K logic elements.

While CPLDs can easily be designed using schematic layouts, FPGAs are often coded in languages such as VHDL. With so many features, fully utilizing an FPGA's capability can be a mammoth task that requires multiple software suites. 

This week, Microsemi announced a new design suite specifically for helping designers navigate the often-complex waters of developing with an SoC FPGA. 

Libero SoC Design Suite V12.0

Microsemi (a subsidiary of Microchip) supplies a wide range of FPGA devices, including the PolarFire, IGLOO2, SmartFusion2, IGLOO, and ProASIC3. This week, they announced the release of Libero SoC Design Suite V12.0.

The design suite offers a runtime reduction of 60% for timing, 25% for place and route, and 18% reduction in power determination times while providing an average increase of 4% in quality for large designs (but 10% increase if a PolarFire MPF300/TS-1 is being used).

While the improvement in placement and routing time has been decreased, what makes the software suite more significant is that all of these latest Microsemi FPGA families are now unified into one design package. Libero SoC V12.0 has also been designed to simplify migration to and from different FPGA platforms.


Libero SoC Design Flow. Image courtesy of Microsemi


According to Rajeev Jayaraman, Vice President of Software for Microsemi's FPGA business unit, the company wanted to ease the design process for engineers and also make it easier for them to adopt Microsemi hardware into their designs in the future: “This latest release [of the Libero SoC v12.0] is focused on delivering the many essential elements needed for efficient design implementation, while further enabling the growing adoption of the low-power PolarFire family across each of our key market segments.”

Features of the Libero SoC include

  • Intuitive design flow
  • GUI wizards guiding through the design process
  • Single-click flow from synthesis to programming
  • Integration of industry-standard third-party tools
  • Rich IP library of DirectCores and CompanionCores
  • Availability of reference designs and development kits


Design Entry using System Builder. Image courtesy of Microsemi


Libero SoC V12.0 also includes FPGA hardware breakpoints for RTG4 and PolarFire devices, PCIe debug capabilities, continuous eye monitoring via SmartDebug, improved DDR memory performance (reportedly up to 29% improved performance), and an Enhanced Tool Command Language (TCL) whereby customers can run an entire design flow in a command line.


Anyone involved with product design knows the importance of getting a product to market as quickly as possible. Product designers also understand and appreciate that FPGAs, while incredibly powerful devices, are complex and require careful handling and planning. Any software suite that unifies multiple platforms into one while improving processing times is something that will be welcome in any engineering department.

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