Polyn Tapes Out First Neuromorphic Analog Signal Processing Chip

Polyn Technology has reached a defining milestone in neuromorphic computing with the tapeout of its first analog signal processing chip based on its proprietary Neuromorphic Analog Signal Processing (NASP) platform. 

Polyn's first taped-out chip leverages an analog neuromorphic core for voice processing applications. Image used under Canva Pro license

Designed for always-on sensor intelligence at the edge, this chip is engineered to process real-world signals with biological efficiency, pushing the boundaries of TinyML in power, latency, and embedded AI adaptability.

Analog Brains for Digital Senses

At the core of Polyn’s innovation is NASP, a hybrid analog-digital architecture that mimics the distributed, ultra-parallel operation of biological neurons. Using analog circuits composed of operational amplifiers and programmable resistors, the system performs inference natively on sensor data, eliminating the need for signal digitization or central CPU involvement at the preprocessing stage.

Conventional sensor data processing versus neuromorphic front-end data processing. 

Polyn built the newly taped-out chip to run a voice activity detection (VAD) model, an edge AI task requiring microsecond latency and microwatt-level power draw. Instead of streaming continuous raw audio to a digital processor or cloud server, the NASP front end filters and compresses the input, outputting only the key embeddings (abstracted feature vectors extracted from signal patterns) that inform higher-level processing.

This front-end intelligence is more than compression: It’s interpretation. By mimicking how the human sensory system relays only meaningful spikes to the brain, NASP enables edge systems to react with speed and efficiency that conventional architectures struggle to match.

A Hybrid Model for TinyML 

The NASP platform is split into two conceptual blocks. A “fixed” portion, implemented as hardwired analog circuitry, handles embedding extraction from raw sensor data. This portion is etched during tapeout and serves as a dedicated feature extractor. The “flexible” portion, implemented in standard digital logic or a low-power microcontroller, performs classification or interpretation based on the embeddings.

This hybrid model embodies transfer learning in hardware. Developers can retrain and adapt only the flexible portion of the model, significantly reducing the design cycle and silicon complexity when deploying variations of similar workloads. For instance, an accelerometer signal interpreted for gait recognition could be repurposed for fall detection simply by modifying the downstream classifier.

The NASP hybrid concept. 

A critical enabler of the NASP platform is Polyn’s proprietary compiler toolchain. It converts trained neural networks—often sparse, irregularly connected structures—into dense analog circuit layouts optimized for area, latency, and power. The compiler applies techniques like pruning and connection minimization to translate high-level models into manufacturable chip topologies with up to eight-bit weight precision using resistor-based synapses.

Polyn’s custom design flow leverages Cadence tools such as Virtuoso and Innovus to marry analog and digital domains in a unified layout. The taped-out NASP chip, fabricated on a 55-nm CMOS process, integrates thousands of analog neurons in a layout purpose-built for scalability and manufacturability.

Embedded Intelligence at Microwatt Scale

Polyn's real achievement, however, lies in NASP’s energy profile. The chip performs signal inference using less than 100 μW, with some implementations, like the NeuroVoice VAD model, operating as low as 30 μW in active mode. This level of efficiency enables always-on sensing in power-constrained environments like earbuds, wearables, smart tires, and predictive maintenance sensor nodes.

NeuroVoice VAD, Polyn's AI chip for voice processing.

By reducing raw data by factors up to 1,000x before it reaches digital logic, NASP front ends also cut bandwidth, reduce cloud dependencies, and improve privacy. In applications like medical monitoring, where every milliwatt and millisecond counts, this architecture can make the difference between feasibility and failure.

A Pathway to Scalable TinyML?

Polyn’s roadmap began in 2019 with a mathematical insight from co-founder Dmitry Godovsky, who developed a method to represent neural inference using analog circuits. Since then, the company has built a deep patent portfolio and secured partnerships with SkyWater, Bridgestone, Infineon, and TDK.

The May 2025 tapeout is the culmination of that vision: a general-purpose, analog-first neuromorphic signal processor that can serve as a hardware foundation for TinyML systems across sectors. While Polyn's initial target application for this chip is voice processing, other use cases may include vibration analysis, biosignal interpretation, and human-machine interfaces.

By shifting inference closer to the signal and reimagining neural networks in analog terms, Polyn’s NASP platform offers a timely, power-efficient model for AI at the edge. As the chip moves through qualification in Q2 2025, it may serve as proof that the next wave of machine intelligence doesn’t need massive compute or constant cloud connectivity; it just needs to listen smarter.