Renesas Hits Milestone for Lowest Power-Consuming BLE SoC

January 26, 2024 by Jake Hertz

Renesas says the new SoC effectively walks the tightrope between on-chip memory and die size.

Renesas recently announced its lowest power-consuming, dual-core Bluetooth Low Energy (BLE) SoC, a feat it attributes to properly balancing on-chip memory and die size. In SoC design, the tradeoff between on-chip memory size and die size significantly impacts device performance and cost.



The DA14592 keeps power consumption low to extend the battery life of IoT devices. Image use courtesy of Renesas

Renesas claims its new chip, the DA14592, strikes this balance at 3.32 mm x 2.48 mm (in WLCSP packaging) and 5.1 mm x 4.3 mm (in FCQFN packaging), making it a worthwhile candidate for applications including asset tracking, human-machine interface devices, smart metering, connected medical devices, crowd-sourced location tracking, and beyond.


Renesas’ Lowest-Power BLE SoC

The DA14592 (datasheet linked) is a multi-core wireless microcontroller SoC featuring an Arm Cortex M33 application processor. It also includes an eight-region memory protection unit (MPU) and a single-precision floating point unit (FPU). Supported by 256 kB of embedded Flash, 96 kB of RAM, and 16 kB of Cache RAM, the processing core can deliver up to 96 dMIPS at 64 MHz.


DA14592 system block diagram

DA14592 system block diagram. Image used courtesy of Renesas

The device supports connectivity with a new software-configurable BLE protocol engine based on an Arm Cortex-M0+. This includes an ultra-low-power radio transceiver with a +6 dBm output power and -97 dBm receive sensitivity, achieving a total link budget of 103 dB​​. The transceiver is designed for high performance, with a single-wire antenna eliminating the need for RF matching or RX/TX switching. This is all achieved at a low power consumption of 2.3 mA transmit current at 0 dBm and 1.2 mA radio receive current.

The SoC offers an array of standard and advanced peripherals, allowing for interaction with various system components and facilitating the development of advanced user interfaces. It supports a real-time clock with 10 ms resolution and has four general-purpose 24-bit up/down timers with PWM capabilities. The DA14592 operates flexibly between 32 kHz and 64 MHz, thanks to its 32-bit Arm Cortex-M33 with an 8-kB, four-way associative cache​.

The device also includes up to 32 general-purpose I/Os, an eight-channel 10-bit SAR ADC, and a ΣΔ ADC with 15 bits at 1 ksps and 13 bits at 16 ksps, featuring a programmable gain amplifier (PGA). 


The On-Chip Memory and Size Tradeoff

Renesas claims its DA14592 effectively balances the constraints of on-chip memory and SoC die size.

Increasing on-chip memory improves the performance and capability of an SoC, enabling more complex software, better data handling, and faster operations. However, adding more memory to an SoC has a direct impact on the die size or the physical dimensions of the silicon chip. Larger dies require more semiconductor material and reduce the number of dies that can be manufactured from a single silicon wafer. This increases the cost per chip due to both the higher material requirements and the reduced yield per wafer. Larger dies can also lower manufacturing yields because of the higher probability of defects, further escalating costs.

A single SRAM cell requires six transistors

A single SRAM cell requires six transistors. Image used courtesy of R. Entner

SoC developers often face the competing interest of adding more memory while also keeping the costs down by minimizing the die size. The balance point depends on the intended application of the SoC. For high-performance applications, such as servers or advanced consumer electronics, larger SoCs with more memory are justified despite the higher cost. In contrast, for IoT devices or basic consumer electronics, manufacturers aim to minimize die size to keep costs low, even if it means having less on-chip memory.

The new DA14592 seems to negotiate this tradeoff, packing in on-chip memory (RAM, ROM, and Flash) while also keeping its bill of materials (BOM) at an all-time low—requiring only six external components. 


Prepped for Low-Power Applications

According to Renesas, the DA14592 is best suited for low-power, connected devices such as IoT, gaming controllers, and activity trackers. The device has already been demonstrated on an electric vehicle instrument panel. The BLE SoC is currently available in mass production and is expected to receive regulatory certifications in the second quarter of 2024.