Renesas Pushes Beyond MRAM Write Challenges Spurring Memory Technology Forward

January 04, 2022 by Jake Hertz

With new improvements to magnetoresistive random-access memory (MRAM) write technology, Renesas claims to improve power consumption for Internet-of-Things (IoT) applications and push MRAM further.

While many memory technologies exist in the industry today, MRAM technology hopes to hold a unique amount of potential, with reports estimating this technology to take off with a CAGR of 25% from now to 2026 and reach $6.2 billion by 2026.

Offering non-volatile memory, low power consumption, and symmetrical and fast read and write speeds, MRAM is thought by many to replace both static random-access memory (SRAM) and dynamic random-access memory (DRAM) technologies eventually. 


A comparison of different memory technologies.

A comparison of different memory technologies. Image used courtesy of Synopsys


Despite its many benefits, the adoption of MRAM technology has been slow due to several challenges, which we'll dive into later in this article.

However, looking to improve MRAM technology to increase its adoption in low power spaces, Renesas recently announced a new MRAM writes technology

In this article, we’ll discuss MRAM technology and the new improvements from Renesas.


Overview of MRAM Technology 

MRAM technology is a relatively new form of memory technology [video] that offers many advantages over traditional memory. 

MRAM technology works by exploiting the fact that the relative polarity of two magnets to one another will affect their electrical resistance. Put more simply, if two magnets are placed next to each other, with one’s north pole touching the other’s south pole, the resistance of the magnetic junction is very low and vice versa. MRAM uses these two resistance states, high or low, to store logic values, 1 or 0.


MRAM cells at both Logic 1 and 0 states.

MRAM cells at both Logic 1 and 0 states. Screenshot used courtesy of Microchip [video]


In general, MRAM claims to offer the advantages of being a non-volatile memory that is fast enough to work as RAM while also offering symmetric read and write times. 


MRAM Challenges 

With MRAM, it can be difficult to tell when a write is completed, resulting in wasted time, energy, and potentially unreliable data states. 

One historical approach uses a self-termination write scheme that uses a comparator circuit to monitor the memory cell and stops the write when it detects completion. However, this solution is not entirely reliable, owing to variation in memory cell characteristics and being limited by the detection accuracy of the comparator circuit.


An example of an MRAM charge pump circuit.

An example of an MRAM charge pump circuit. Image used courtesy of US Patent NO20060239056


Another challenge has been that, historically, MRAM write voltages have been determined by the worst bit write characteristics in the memory cell characteristics variation (i.e., scaling up the write voltage to accommodate the worst-case scenario). 

This requirement caused MRAM cells to use relatively large write voltages, resulting in the need for a dedicated charge pump circuit to generate these voltages. Additionally, this extra circuitry takes up space and power, and solutions to mitigate this result in increased MRAM write times. 


Renesas Tackles Memory Write Challenges

Recently, Renesas has announced that they have developed solutions to the MRAM challenges, namely those mentioned previously, both of which work to save power in MRAM technology. 

To solve the challenge of write-completion detection, Renesas has proposed that, instead of applying fixed voltages during write operations, they should instead apply a slope voltage which gradually increases over time. 

Using this method, even if the memory cell current doesn’t reach a level high enough for detection, the continually rising slope voltage ensures that the memory cell current eventually exceeds the detection level. 

Additionally, to solve the issue of large write-voltages, Renesas recognized that designers could reduce these voltages by allowing failure bits up to 10%. 

Essentially, the technique consists of first writing all bits with a very small write voltage and then following up on ~10% of failed bits with a large, charge-pump voltage. In this technique, most bits don’t require the power-intensive charge-pump voltage, saving time and power in the application. 

Overall, by combining these two techniques, Renesas reported reducing write energy by 72% and shortening write times by 50% in a 20 Mbit MRAM cell.


Paving the Road for MRAM 

With these advances in MRAM technology, Renesas hopes to enable future low power in microcontroller units (MCUs) with applications such as IoT to leverage MRAM technology. 

As the need for better and lower power memory becomes a need, not a want, the road towards MRAM technology looks promising, with companies like Renesas taking on its design challenges. It will be interesting to see where this technology heads in the future and where companies such as Renesas will take it.