Researchers Rethink Computer Vision With All-Analog Photoelectronic Chip

November 13, 2023 by Duane Benson

An all-analog photoelectric chip promises to be three orders of magnitude faster and six orders of magnitude more energy efficient than existing processors.

Accurate computer vision recognition is a requirement for the next generation of AI-assistant technology. Vision systems will be installed for far more applications than just security and navigation. With today’s technology, vision recognition requires power-hungry GPUs and high-speed CPUs.

A research team at Tsinghua University, China, is developing an integrated analog photoelectric processor they call an "all-analog chip combining electronic and light computing", or ACCEL chip. 


The ACCEL team at Tsinghua University

The ACCEL team at Tsinghua University. Image used courtesy of Xinhua


The team created this chip in response to the dramatic increase in computing power required by the next-generation vision AI.


A New Approach to Photonics and Analog Computing

The ACCEL project at Tsinghua, published in Nature, aims to address this power challenge with a unique combination of analog electronic and optical computing.

The Tsinghua team believes analog computational devices can process photoelectric data faster and more efficiently than conventional photo sensors by several orders of magnitude. This is because analog computing can be less complex while maintaining speed and low energy consumption; you can even perform floating point math with a single op-amp. Analog's big disadvantage has always been its level of accuracy.

That paradigm may be changing. New semiconductor materials have greater purity and have more predictable behaviors. Sundry components also come with higher precision. The result is applications—like image recognition—where analog electronics can be accurate enough, with a faster speed and lower power consumption than digital. In addition, modern analog computing negates the need for an initial ADC stage and enables much faster analog calculations.


The Architecture of the ACCEL Chip

Traditional vision systems start with an optical sensor that first translates the RGB values to digital numbers. That set is processed as a massive array with neural net processing in GPUs, CPUs, or other high-end processing systems. With ACCEL, the main goal is to reduce the complexity of the image with optical processing and analog computing prior to the ADC stage.  


Traditional ADC heavy digital recognition system and the ACCEL system

Traditional ADC-heavy digital recognition system (a) and the ACCEL system (b). Image used courtesy of Nature

The optical analog layer (OAC) is physically layered in front of the electronic analog computing (EAC) layer to deliver a single-chip solution. This chip puts weighted numbers into an SRAM array. The OAC layer uses diffractive optical computing as a preprocessing stage. The lensing array in the OAC layer effectively acts as a large set of analog Fourier transformation processors. No power is required in the initial optical layer. Optical processing also happens nearly instantly.

With the image reduced through the OAC, a smaller analog photodiode array converts the optical information into a set of analog electronic signals. The chip in the research project has 32 x 32-pixel arrays. Each pixel has an analog photodiode, three switches, and an SRAM macro to store the weighted values. The weighted value is used to control the switches and route the analog photodiode output appropriately. The routing sends the difference between the initial set voltage and the photodiode output to a comparator used to determine the data classification based on the MINST dataset. 

The ACCEL system has been shown to recognize images with 98% fewer ADCs than conventional digital recognition systems. The team has also tested the experimental chip against other datasets with equally positive results. 

To date, the team has worked with fairly small image arrays, but they project that the design is scalable by adding additional OAC layers, increasing the photodiode sensitivity, or increasing the number of bits in the SRAM macro.


Keeping Moore’s Law Alive

It has been said many times that Moore’s Law is dead and gone. It may be nearly so in conventional silicon digital electronics. But by reevaluating other computing topologies, including some from the past, like analog computing, the spirit of Moore looks to be nowhere near its ends.

Devices like ACCEL use different techniques than digital brute force to radically increase computation while decreasing energy consumption. These techniques may allow AI, image recognition, and other power-hungry applications to continue at a rate that would likely leave Gordon Moore satisfied.



Featured image (modified) used courtesy of Xinhua.