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RISC-V Shines at Embedded World With New Specs and Processors

3 days ago by Jeff Child

At Embedded World 2022 today, RISC-V activity heats up as RISC-V International reveals four new spec approvals and SiFive unveils a new version of its X280 processor.

Our coverage of Embedded World 2022 continues with multiple announcements today centered around RISC-V technology.

Today RISC-V International has announced four specification approvals, the first of 2022. These include the RISC-V E-Trace, RISC-V SBI, RISC-V UEFI specifications, and the RISC-V Zmmul multiply-only extension. Meanwhile, today SiFive, the founder of RISC-V computing, has released a new version of its SiFive Intelligence X280 processor.

 

Table 1. Summarized here are the four specifications newly ratified, and the RISC-V task groups responsible for each. Information used courtesy of RISC-V International

Summarized here are the four specifications newly ratified, and the RISC-V task groups responsible for each.

 

In this article, we review the four new RISC-V specifications, share analysis from our interview with Mark Himelstein, CTO of RISC-V International, and examine the details of SiFive’s new version of its X280 RISC-V processor.

 

First Four RISC-V Specs of 2022

The open-standards organization RISC-V International had a busy 2021 with 16 specifications ratified representing over 40 RISC-V extensions. Today, the group is building on those achievements, with four new specifications and extension approvals announced at the Embedded World show. Also included in the announcement was a notice that six more specifications are in the pipeline aimed at vertical applications.

We’ll examine each of the newly approved specs. Each (except Zmmul) has a full GitHub page with resources for each specification.

First up is the E-Trace for RISC-V specification. It spells out an efficient method for processor tracing. The scheme uses a branch trace, which the group says is ideal for debugging any type of application—ranging from small tiny embedded designs to high-performance computers. 

Documentation for the spec specifies the signals between the RISC-V core and the encoder (or ingress port), a compressed branch trace algorithm, and a packet format to encapsulate compressed branch trace information. Himelstein says that E-Trace is a vital RISC-V capability for tasks such as debugging, troubleshooting, and board bring-up.

The second spec, RISC-V for Supervisor Binary Interface (SBI), sets up a firmware layer between the hardware platform and the OS kernel. This is implemented as an application binary interface in supervisor mode (S-mode or VS-mode). Abstracting that way allows common platform services across all RISC-V OS implementations.

SBIs fill an important role. “I don't care if you're talking about an earbud all the way up to a data center computer,” says Himelstein. “You can’t implement a system unless you have some interface between the operating system and the hardware.”

 

"System binary interfaces (SBIs) enable operating systems and hypervisors to do their job without knowing the nitty gritty details of the implementation. SBIs are also what security features are built on, because you don’t want to give direct access to what you’re booting out of, such as root-of-trust or something like that."

 

Specs Ratified for UEFI and “Multiply Only” Efforts

The third RISC-V effort that’s part of today’s announcement is the RISC-V UEFI Protocol spec. This document carries existing UEFI standards onto RISC-V platforms.

Himelstein views the UEFI spec as somewhat similar to the SBI spec. The difference is UEFI (Unified Extensible Firmware Interface) is based on the industry standard of the same name. “We worked with the upstream UEFI project to figure out what the right thing was for RISC-V,” he says, “We vetted our approach with them (the UEFI Forum) before we went ahead and approved it on our side.”

Finally, the RISC-V Zmmul Multiply Only involves a relatively simple, but important change. Actually, as part of the RISC-V Unprivileged Specification, Zmmul enables the implementation of low-cost applications that require multiplication operations but not division.

According to Himelstein, the problem that the Zmmul addresses come from feedback from the embedded community. The divide is used so infrequently, that it makes sense to separate it out. “Having multiply and divide together was not what the embedded world was looking for,” he says. “They want to just multiply, and so this splits them up.”

 

Focus on RISC-V Ecosystem Enters Full Swing

Himelstein points out that these new spec efforts contrast with RISC-V’s 2021 spec ratification work in that last year was all about RISC-V instructions and instruction-related specifications. “All that time, we were also working on all these other things that we’re announcing today and in the future,” he says. “And none of those happened overnight.”

 

"It took a little longer to get some of these things (specs) in place. But at this point, I'd say we're about at a one-third/two-thirds mix—where one-third is instruction-set related things, and two thirds revolve around the software ecosystem and the hardware/software handshake. This includes SoC support, security, operating systems, hypervisors, compilers, etc. So it's very exciting. We have 66 groups now working on various pieces of RISC-V technology."

 

SiFive X280 Processor Upgrade Aims at Vector Processing

Switching gears to SiFive’s Embedded World announcement, today the company unveiled the latest version of its SiFive Intelligence X280 processor. The original X280 version has been available since April 2021, and the new enhancements are based on customer feedback. According to the company, the new version of the processor IP adds major features.

The new features include:

  • Scalability up to a 16-core cache-coherent complex
  • A SiFive implementation of “WorldGuard” protection
  • A new interface called VCIX (Vector Coprocessor Interface eXtension)

The new enhanced X280 is a multi-core and multi-cluster capable RISC-V processor that offers full support for the RISC-V vector extension standard and SiFive Intelligence Extensions. It is optimized for AI/ML compute at the edge, targeting applications such as AI inference, image processing, datacenter acceleration, and automotive.

 

SiFive’s Intelligence X280 processor offers an multi-cluster scheme comprising up to 4 clusters of 4-core complexes.

SiFive’s Intelligence X280 processor offers a multi-cluster scheme comprising up to 4 clusters of 4-core complexes. Image used courtesy of SiFive

 

The X280 offers a “multi-cluster” architecture that features up to 4 clusters of 4-core complexes. According to SiFive, the VCIX is a vector coprocessor accelerator interface that makes it easy to integrate with customer AI architectures. This includes a wide and growing crop of third-party accelerators. VCIX smooths the way for easy-to-program, low latency data movement between customer-owned AI accelerators and the host processor, says SiFive.

Finally, WorldGuard Ready is SiFive’s implementation of the open standard WorldGuard security environment. The technology provides a trusted execution environment suited to high core count platforms. It can protect AI/ML algorithms against malicious attacks.

More information is available in the SiFive Intelligence X280/X280-MC datasheet.

 

Big RISC-V Presence at Embedded World This Week

Clearly, the RISC-V technology ecosystem is moving forward at a rapid pace. And because RISC-V is so well suited to the “customized” world of embedded systems, it’s no surprise that this week’s Embedded World trade show is where stakeholders choose to make these major announcements. For its part, RISC-V is the theme of several talks at Embedded World this week.