SiFive Adds Flex Logix eFPGA IPs to DesignShare Initiative
SiFive, the company behind the first RISC-V based SoCs, has recently announced the addition of Flex Logix’s FPGA IP to its DesignShare initiative.
SiFive, the company behind the first RISC-V based SoCs, has recently announced the addition of Flex Logix’s FPGA IP to its DesignShare initiative.
The DesignShare initiative seeks to remove barriers and streamline access for small companies developing customized SoCs, allowing them to incorporate existing IPs into their prototypes, and getting new designs to market faster. This is achieved through access to IPs at deferred, low, or no cost by DesignShare collaborators. AllAboutCircuits reported on Rambus joining DesignShare this past August.
The new arrangement brings together SiFive’s Freedom U500 28nm platform with Flex Logix’s EFLX embedded FPGA (eFPGA) which will be available in different sizes. This fuses together the open-source RISC-V instruction set architecture with the EFLX eFPGA’s customizable accelerator properties.
The Freedom U500 is designed to support custom accelerators with coherent access to the L2 cache, DRAM, and the ability to generate or receive interrupts from the interrupt controller on the platform. An upcoming tape out of the U500 will include the EFLX eFPGA on the TL-bus and up to 64 GPIOs. U500 evaluation boards and software will be sent to customers for feedback.
SiFive U500 Architecture. Image courtesy of SiFive.
SiFive Freedom U500 Specs:
- U5 Coreplex with 1-8 64bit RISC-V cores with private cache and shared L2 cache
- DDR3/DDR4 DRAM channels
- PCIe 3.0
- 1 Gb Ethernet
- USB 3.0
The EFLX eFPGA
The EFLX eFPGA is different from a traditional FPGA in that it is an FPGA core integrated into a chip, removing the need for high-speed SERDES, GPIO buffers, PLLs, and proprietary bus interfaces.
Typical FPGA vs Embedded FPGA. Image courtesy of Flex Logix.
Flex Logix also has a patented architecture which reports a higher efficiency than traditional FPGAs. In a traditional FPGA, more than 10 metal layers might be used in a 2D mesh architecture, with approximately 70% FPGA utilization, and up to 80% of the FPGA fabric being used for interconnecting logic blocks. In the 1st generation EFLX architecture, only 5 or 6 metal layers are used, achieving up to 90% FPGA utilization, and 60% of the FPGA fabric being used for interconnecting logic blocks. The reduced amount of metal layers also adds to the increased modularity of the eFPGA.
The increase in interconnection efficiency is achieved using a Boundary-Less Radix Interconnect Network, a solution devised by the company’s co-founder, Cheng Wang, who decided to focus on developing a better interconnect method during his Ph.D. This method, which was published in a paper at the International Solid-State Circuits Conference 2014, won the Outstanding Paper award, often handed out to large silicon companies like Intel.
The EFLX eFPGA is programmed using Verilog or VHDL, and then run through the Flex Logix compiler. A demonstration is given in the video below.
On the Flex Logix website, various core IP options are available including rad-hard eFPGAs—a useful option for space applications. Flex Logix is certainly a unique addition to the DreamShare initiative, and it will be interesting to see what comes out of this collaboration.
Feature image courtesy of Flex Logix.
