RISC-V continues its trajectory into popularity as the RISC-V Foundation continues to make partnerships with academia and companies across the industry.

The RISC-V Foundation has continued to build on its momentum, announcing the open-source ISA presence at HOT CHIPS 29—a symposium focusing on high-performance processors and integrated circuits held annually in Silicon Valley in mid-August. Speaking presentations, an exhibit, and a poster presentation gave audiences insight into the current progress and ambition of the foundation’s goals. 

 

SiFive Freedom and Rambus Partnership

SiFive was the first company to produce chips specifically for the RISC-V architecture. Launching its first crowd sourcing campaign in 2016, SiFive sought to put RISC-V into the hands of hobbyists and commercial companies alike, offering pre-packaged or customized solutions. 

Last week, SiFive announced a new partnership with Rambus, a semiconductor company with a broad range of products in memory, smart sensors, and security. In this particular partnership, Rambus will be providing SiFive with cryptography cores which will be implemented on the SiFive Freedom Chip to enhance security, particularly for IoT applications.

The partnership with Rambus is the first in what SiFive says will be many other partnerships, as part of the DesignShare IP sharing scheme. DesignShare helps facilitate partnerships with emerging semiconductor and custom-silicon companies through low cost or no cost IP sharing. This speeds up engineering and design of new products or platforms, making new and interesting possibilities available sooner. 

 

Celerity: Using RISC-V to Speed Up Development Time

Celerity is an SoC produced by researchers from the University of California San Diego, University of Michigan, Cornell, and UCLA. It's described as “the first open-source, RISC-V tiered accelerator fabric system on chip with a neural network accelerator and 511 RISC-V processor cores”. The presenters claim that Celerity is the “most complex chip ever created in academia."

The Celerity has five RISC-V cores, with a 5x5 mm chip hosting 360 million 16nm transistors, a 625 MHz biniarized neural network, and an NOC-connected manycore consisting of 496 RISC-V cores.

The team credits RISC-V as enabling the researchers, some of them only first or second year graduate students, to complete and speed up the complex SoC design, and reduce the overall cost. From prototype to fabrication, it took 9 months and $1.3 million, which is a trivial in the SoC industry.

The inspiration for the Celerity came from a 2016 CERTUS initiative (a DARPA program), which funded projects to reduce SoC design time by a factor of 10 (16 weeks down from 160 weeks for current industry expectations). 

 

CERTUS is a DARPA initiative to speed up SoC design. Image courtesy of UCSD.

 

The intent of the Celerity is for future use in autonomous cars, where using the neural network accelerator will aid in processor sensor data faster. After all, speedy decision-making by a system is critical in autonomous navigation and driving.

 

Codix Berkelium: RISC-V and ASIPs

Codasip is a Czech based company specializing in application specific instruction set processor IPs and tools. The company began research efforts in 2006 before launching in 2014. 

Codasip has four processor families. Their Codix Berkelium family, specifically, is RISC-V compatible and have the following features:

  • 3 and 6 stage pipelines
  • Support for RV32IM and RV64IM
  • Compact instruction set support
  • Configurable general purpose registers
  • Configurable branch prediction unit
  • Interrupt support
  • JTAG support
  • Sleep Mode support
  • Optional floating point (and instruction and data cache)

The Codix BK also makes use of WalnutDSA algorithm from SecureRF, which is a fast, low energy security “quantum resistant” algorithm.

 

WalnutDSA diagram. Image courtesy of SecureRF.

 

GRVI Phalanx: RISC-V for Software-Based FPGA Acceleration

The GRVI (pronounced “groovy” and stands for “Gray Research RISC-V RV”) Phalanx was first introduced in January 2016 by Jan Gray. It makes use of clusters of softcore processors and clusters of accelerator cores to expand on the performance of FPGAs through parallel processing. 

One of the fundamental principals of the framework is stripping away all unnecessary functions of a processor and minimizing look-up-tables.

Watch the video below to learn more:

 


To get more background information on the evolution of RISC-V, check out "Is 2017 the Year RISC-V Will Catch-On?"

 

Feature image courtesy of SiFive.

 

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