sureCore’s Low-power Memory IP to Expedite Power-critical Designs
sureCore’s off-the-shelf memory products integrate power-saving features for battery-critical designs like wearables and hearables.
Low-power electronics are essential for increasing battery life and improving the overall sustainability of electronic devices. This is particularly important in mobile devices such as smartphones, wearables, and hearables. One of the top sources of power consumption in these devices is memory hardware, which is tasked with faster speeds and greater capacity.
This week, sureCore announced an array of off-the-shelf memory IP designed to ensure ultra-low power in wearables and hearables.
Independent banks in sureCore's EverOn SRAM. Image courtesy of sureCore
In this article, we’ll discuss why memory is such a pressing design concern in a power-conscious IoT environment and how sureCore is hoping to address this challenge with low-power, off-the-shelf offerings.
Memory and Power
Memory is a major contributor to wearable power consumption. In modern fitness trackers, a plethora of sensors tracks health biometrics and activity. This reliance on sensor data creates a high demand for device memory to store and read out the mass influx of data. These constant read-and-write operations required to store and retrieve data result in high power consumption from memory devices.
As wearables become more highly integrated with advanced sensing technology and are expected to operate at faster clock rates, memory is only expected to become a larger contributor to overall device power consumption.
EverOn for "Always On" Devices
To address this issue, sureCore has released EverOn embedded SRAM, designed for “always on” solutions. EverOn features a single-port, single-voltage rail synchronous SRAM with a hierarchical bit line architecture and a set of finely-grained sleep modes. These sleep modes are said to allow for significant power savings of up to 70% dynamic and up to 60% static/leakage compared to other SRAM solutions.
The EverOn architecture. Image courtesy of sureCore
EverOn's advanced sleep modes enable one or more memory banks to be shut down, creating additional power savings without splitting one large memory into several smaller instances. The periphery can also be placed into low-power mode to achieve even lower power consumption. EverOn is also highly configurable, supporting word lengths from 16 to 72 bits and up to 576 Kbit max instance size.
One of the key features of EverOn is its "Smart Assist" technology, which controls voltage drive to selected bit cells and bit lines during read and write cycles. Additionally, the memory array incorporates a pre-charge, mux-sense read circuit to help reduce both active and leakage power. EverOn supports configurable global data mux and programmable sleep modes, including light sleep, deep sleep, and shutdown, on an individual bank basis.
In addition to EverOn, sureCore offers another low-power memory solution, PowerMiser. PowerMiser is a single-port, synchronous, low-power SRAM IP designed for energy-efficient SoC systems across various market applications. The patented architecture includes a compiler technology, which is said to reduce dynamic power by over 50% and static/leakage power by up to 20% compared to other SRAM solutions.
The PowerMiser architecture. Image courtesy of sureCore
This technology is available for 28 nm and 22 nm process node designs and scales down to 16nm and 7nm FinFET. PowerMiser comes in standard and low-leakage versions, with an operating voltage of 0.9 V +/-10% at 28 nm and 0.8 V +/-10% at 22 nm. It has a retention voltage of 0.55 V in 28 FDSOI, 0.63 V in 28 HPC+, and 0.6 V in 22 ULL. Configurable word length is up to 144 bits, while 32- or 64-bit lines are available. Additionally, programmable sleep modes, including light sleep, deep sleep (data retention), and shutdown, are supported.
The solution has a maximum instance size of 576 Kbit, configurable into 4Kx144, 8Kx72, or 16Kx36. The technology also has APTG and BIST support and works seamlessly with industry-standard EDA design flows.