Synopsys’ Die-to-Die PHY IP Speeds Up Cloud Computing SoC Designs

November 01, 2019 by Lisa Boneta

The die-to-die PHY IP enables extra-short reach connectivity in multi-chip modules (MCM) for hyper-scale data centers, AI, and networking applications.

Cloud computing has made storage, servers, and applications readily available for billions of people. With the rapid and continuous increase of users on various Internet platforms and services, finding a way to optimize the speed, power, and performance of the cloud is a priority for engineers. 

Optimizing SoC designs can incite major improvements in the design process and the end product.


DesignWare Die-to-Die PHY IP for Cloud Computing SoC Designs 

Synopsys recently announced DesignWare Die-to-Die PHY IP as the newest addition to their comprehensive cloud computing IP solution; the IP portfolio includes 112G/56G Ethernet HBM2/2E, DDR5/4, PCI Express 5.0 controller, PHY, and verification IP.


DesignWare Die-to-Die PHY IP

DesignWare Die-to-Die PHY IP. Image from Synopsys


The new design allows for high-bandwidth, ultra- and extra-short reach connectivity in multi-chip modules (MCM) for hyper-scale data centers, AI, and networking applications.


Key Features

Some key features of the DesignWare Die-to-Die PHY IP include its ability to:

  • Deliver less than 1 pJ/bit for ultra-low-power die-to-die and die-to-optical engine connectivity
  • Compact analog front-end for reliable links of 50 mm for large MCMs
  • Support NRZ and PAM-4 signaling from 2.5G to 112 G data rates


Overcoming Maximum Reticle Size

SoCs have approached many limitations as the need for overall improved performance has increased. One limitation that the die-to-die design helps overcome is the maximum reticle size. Because larger dies are partitioned into smaller segments on the chip, having reliable die-to-die connectivity between several chips is extremely important.

It’s also important to note that the splitting of larger dies into smaller dies is used to improve yield (the measure of the percentage of dies on a wafer that is not discarded during manufacturing), which is exactly what is done with the DesignWare Die-to-Die PHY IP.

However, the DesignWare Die-to-Die PHY IP is limited to use for 7nm FinFETs. With such a development, an extension to 5nm and 3nm chips may be the next stride.


Beyond the Cloud 

Such an advancement can also be useful for edge computing, such as with the Internet of Things (IoT) devices. Unlike cloud computing, edge computing allows for data processing mainly on the device itself. Computing at the edge rather than in a cloud allows users to save time, bandwidth, and money while decreasing overall latency. SoCs are being used more often for edge computing and have helped improve these metrics.

While Synopsys doesn’t mention edge computing as a specific target application, the improvements that DesignWare Die-to-Die PHY IP offers are necessary for many performance metrics in edge applications.


More on DesignWare

DesignWare IP offers comprehensive IP solutions for SoC designs that include logic libraries, embedded memories, embedded tests, analog IP, analog interface, and more.

 DesignWare Die-to-Die RX and TX block diagram

Block diagram of DesignWare Die-to-Die RX and TX block diagram. Image from Synopsys

Additionally, to accelerate product development cycles, Synopsys’ IP accelerated initiative offers SoC architecture design support, IP subsystems, and comprehensive silicon bring-up support. 



Does cloud computing play a role in your SoC design process? Share your experiences in the comments below.