Targeting Automotive, Infineon Spins Industry’s First LPDDR Flash Memory
To meet the new demands of automotive zonal architectures, Infineon marries flash memory with an LPDDR interface to enable more performance and scalability than xSPI NOR flash.
As cars move to software-defined vehicle architectures, next-gen designs are facing a memory problem. For a host of reasons, traditional xSPI NOR flash memory won’t cut it. To address these needs, today Infineon Technologies has announced the industry’s first LPDDR flash memory.
Called the SEMPER X1, this new flash memory device borrows the LPDDR interface scheme from the well established 10-year old LPDRR4 DRAM and applies it to flash memory.
SEMPER XI borrows the LPDDR interface scheme from the DRAM world in order to meet emerging computing needs in automotive.
In this article, we discuss the problems LPDDR flash was developed to solve, we examine the benefits of the new technology, and we share perspectives from our interview with Sandeep Krishnegowda, vice president of marketing and applications at Infineon.
Performance and Density Memory Demands for Automotive
According to Krishnegowda there is both a need for more flash memory and faster performance flash memory in next-gen autos. The shift to zonal architectures in cars calls for real-time processing that requires more performance that what today’s standard NOR flash memories can offer.
Domain and zone controllers consolidate many safety-critical functions, and must process huge amounts of data in real time. (Click on image to enlarge)
As the diagram above shows, these new car designs have zone controllers (in green) throughout the vehicle. “These zone controllers have a lot of real-time computing needs,” says Krishnegowda. “They don’t just pass along this data to the central ECU. These zone controllers need to handle safety critical functions like the braking, the steering, and the powertrain.”
To be able to handle these real-time processing needs, automotive zonal controllers have had to keep pushing to higher performance levels. “Where 4K DMIPS was common, now zone controllers are going to 10K, 12K, and 16K DMIPS,” says Krishnegowda. This more complex computing goes beyond what a controller with on board internal embedded flash can handle.
The Need for Faster External Flash Access
The computing needs in next-gen automotive designs have pushed a move away from real-time processors with few CPU cores and on-board flash. These are being replaced with high-performance multi-core processors with no embedded flash.
Indeed, at the advanced semiconductor process nodes used by those processors, adding on-board flash isn't cost effective because of the mismatch between processor and memory in terms of their semiconductor technology advancement.
The demands of next-gen automove designs call for a shift to fast real-time multi-core processors that execute from external flash memory.
At advanced process nodes, automotive-qualified embedded flash technologies are challenged by high cost (die area) and lack of scalability. All that is combined with the fact that more flash memory is needed to support growing code size and complexity in automotive. And, on the interface side, standard xSPI NOR flash fails to meet real-time execute-in-place (XiP) performance requirements.
It was with all that in mind that Infineon created this new category of memory called LPDDR flash. “We worked with some of our Tier 1 OEMs to define this category of LPDDR flash to address this problem of the growing need for real-time compute for execution with multicore CPUs,” says Krishnegowda. “In LPDDR flash, you have multiple banks of memory so that, when you have multiple cores, any of the cores could talk to any of the banks because it's a random access in nature.”
Krishnegowda says that this categorically improves execution speeds. “If you compare this to a standard Octal (x8) xSPI NOR flash device, moving to an LPDDR flash gives you 20x higher performance,” he says. “This is what's needed in order for you to move what used to be computed inside the processor to instead being computed in external memory in real-time.”
The SEMPER X1 flash can provide up to 3.2 GB/s of throughput with its LPDDR interface. Its multi-bank architecture supports over-the-air firmware updates with zero downtime, according to the company. Importantly, the device is ISO26262 ASIL-B compliant and offers advanced error correction and other safety features.
xSPI Can’t Keep Up and Can't Scale
Among the important factors driving the need for LPDDR flash is that it’s replacing xSPI, an interface that is not only two slow now, but can’t scale for future needs. “If you think about a standard Octal SPI device today, it runs at 200 MHz and uses a LVCMOS I/Os, and you can't scale that more than 200 MHz,” says Krishnegowda. “So if you want higher bandwidth, I have to go towards a new memory standard.”
When considering the options available, Krishnegowda says that they didn’t see standard DRAM, HPM (HyperDRAM), or GDDR DRAM as having the right performance for these applications. “What we needed was in line with what the industry had already developed with an LPDDR4 DRAM,” he says.
Today’s xSPI NOR flash is too slow now, and can’t scale beyond 200 MHz. Meanwhile, LPDDR4 interface offers the scalability and performance required for direct code execution from external flash devices. (Click on image to enlarge)
“We also chose LPDDR4 for scalability—it can actually go down to a x8 single channel device, or it can actually go to having two channels—channel A and channel B—with a x16,” says Krishnegowda. “That gives us enough scalability there to enhance this generation of products to new performance levels.”
Meanwhile, Krishnegowda points out that today's standard Octal xSPI flash devices are not good for code execution. “You can execute code at a very low frequency, but when you're talking gigahertz multicore processors, you cannot execute because you need to pipeline a lot of your address information to get the next data as quickly as possible,” he says.
Unfortunately, SPI makes you provide a command whether you're reading or writing. And then you have to repeat that all over again each time in a very sequential way so you're not pipelining. In contrast, the LPDDR4 protocol lets you split commands and addresses from your data. That lets you do a lot of pipelining, reducing your latency cycles and and allowing quick access to the data.
Infineon says that SEMPER X1 is sampling now with commercial availability planned for 2024.
All images used courtesy of Infineon