TSMC Reveals Ambitious Plans for Its 4nm and 3nm Processes

Later this year, Apple, one of TSMC’s oldest and largest customers, is expected to debut the first large-scale, mass-produced 5nm processor with the A14 chip. It’s also likely that when Apple begins producing its first Macs with its own silicon, also later this year, its processors will also be based on TSMC’s new 5nm process node.

 

Rendering of one of TSMC's 5nm facilities, Fab 18. Image used courtesy of TSMC

 

It makes sense then for TSMC to begin providing details about the successor to its N5 process, N4, and that’s what the company did at its annual Technology Symposium on August 25. TSMC also provided some details about its subsequent N3 process.

 

What’s on the Horizon? 

Prior to announcing the company’s plans for N4, TSMC said that there are plans underway to implement an enhanced version of the N5 node called N5P. This version will come in 2021 and, according to TSMC, will provide roughly a 5% speed gain and 10% power improvement over N5 as it currently stands.

 

TSMC says the N5P will trump the speed of the N5 by 5% and power by 10%. Image used courtesy of TSMC

 

In terms of N5’s generational successor, TSMC said that the migration to N4 will be a “straightforward” one and act as an extension of N5 with some notable power, performance, and density improvements. To aid migration, N4 will be able to leverage the 5nm design ecosystem. In regard to density, TSMC promised that it will be able to somewhat reduce the number of mask layers.

TSMC did not provide any figures or promises so far as performance gains are concerned, only that it’ll provide further improvements in the areas already mentioned to “cover a wide range of product needs.” TSMC also more or less admitted that N4 will be more along the lines of an incremental advance rather than a “generational leap." This will come with N3. 

 

Looking Ahead to N3 in 2022

According to TSMC, the N3 process is on track to become the most advanced logic technology in the world featuring up to 15% performance gain, up to 30% power reduction, and a logic density gain of up to 70% over N5. These gains are more in keeping with the large gains typically seen with TSMC’s generational jumps, for example, the jump from N7 to N5 where logic density increased by 1.8 times. 

 

TSMC's schedule for major R&D projects. Image used courtesy of TSMC

 

Despite Samsung’s 3nm process node making use of gate-all-around transistor structures, TSMC will surprisingly stick with FinFET transistors with N3. The rationale for sticking with this technology is that TSMC customers are apparently comfortable with the promised performance improvements made possible by “innovative features,” which will enable TSMC to achieve full-node scaling with N3. 

The N4 process is scheduled to start risk production in the fourth quarter of 2021, with volume production in 2022. TSMC aims to start initial N3 runs in 2021 with volume production to follow in Q3/4 2022 at the earliest.