VISC: The New Coprocessing RISC-V Architecture for AI Efficiency

April 12, 2024 by Duane Benson

The VISC architecture, developed by UK-based Red Semiconductor, targets AI autonomy, cryptography, and other AI applications

Red Semiconductor has announced the availability of its Versatile Intrinsic Structured Computing (VISC) architecture for RISC-V. VISC is an extension to RISC-V IP that accelerates complex algorithms and adds parallel processing to improve AI operations in edge computing.


Red Semiconductor CEO James Lewis

Red Semiconductor CEO James Lewis. 

One of RISC-V's strong value points is the amount of customization possible within the standard. Red Semiconductor has taken advantage of that aspect to develop a licensable high-performance architecture. The VISC instruction set architecture (ISA) adds edge AI, autonomy, and cryptography capabilities to open-source RISC-V. The code is optimized for FPGA and ASIC SoCs.


What Is VISC?

VISC is a vector processing engine built within a RISC-V processor chip. It has its origins in open-source Libre-SOC. Libra-SOC is designed to bring complex algorithms, typically reserved for GPUs, to microcontrollers and small CPU-based devices. Red Semiconductor built VISC upon Libra-SOC and the open-source CPU RISC-V architecture. The result is a CPU core that is compatible with RISC-V and has vector AI processing extensions.

Red Semiconductor claims VISC performs higher and with less power than other small system/high computation-need processing devices. It improves performance by using hardware elements to deconstruct algorithms into blocks optimized for parallel processing.


VISC strengths

VISC strengths. 

The VISC RISC-V processors purportedly deliver up to 100x efficiency in algorithms typically used in AI and machine learning and other highly complex math operations like cryptography and codecs. It relies on a single-issue multi-execute architecture and memory-efficient 64 x 128 deep byte-accessible registers to reduce power consumption. The system breaks algorithms into smaller parts that can be executed in parallel without synchronization issues that often occur in parallel processing. By doing so, large computations can take considerably less time and use less power.



Developers have added CPU cores to FPGA and ASIC chips for quite a while, with Arm cores being one of the most popular. However, FPGA and ASIC developers relying on Arm are at the mercy of the speed of Arm product releases. Because RISC-V is open source and adaptable, it is a popular alternative for developers who want to advance SoC offerings faster. With AI taking the world by storm, FPGA and ASIC device developers can’t wait, and that’s where Red Semiconductor comes in. 

Red Semiconductor launched in 2021 to jump on both the RISC-V and AI bandwagons. Backed by the ChipStart UK incubator, the Red Semiconductor founders saw the increasing need for edge AI computing and more flexible AI options for FPGA and ASIC developers. VISC is their answer. 


Red Semiconductor and global computing challenges

Red Semiconductor and global computing challenges. 


VISC brings accelerated AI capability to FPGAs and ASICs that need RISC performance and flexibility. As an IP design, it can be used both as a soft processor core added to an FPGA configuration and as hard silicon in an ASIC. As a RISC-V augmentation, VISC brings optimized AI and heavy-duty math computing capabilities to the FPGA, ASIC, and SoC worlds. 


VISC Heading for the Real World

If 2023 was the year of cloud-based generative AI, 2024 will be the year of edge AI. This technology requires more power in remote devices, however. Cars, smartphones, medical devices, industrial controls, and other products in the field need to process, interpret, make decisions, and act without taking the time to route data to and from the cloud.

VISC gives developers the option to add highly AI-optimized RISC-V to their edge devices while remaining conservative with their power and cost budgets.



All images used courtesy of Red Semiconductor.