A Rundown of x86 Processor ArchitectureJanuary 02, 2016 by Donald Krambeck
x86 processor architecture is coded in a language known as Assembly. Assembly language is a great tool for learning how a computer works, and it requires a working knowledge of computer hardware. This article will detail basic microcoputer design, instruction execution cycles, how memory is read, and how programs run.
Basic Design of Microprocessors
Although the subject of this series of articles is based around using the Assembly Language for x86 Processor Architecture, some background information pertaining to x86 processors will be helpful. This is the first in a series.
The central processor unit (CPU), is where calculations and logic operations all take place. The CPU contains a finite number of storage locations, or registers, a high-frequency clock, like a control unit, and an arithmetic logic unit.
The clock synchronizes the internal operations of the CPU with other components in the system.
The control unit (CU) arranges the sequencing of steps involved in executing system instructions.
The arithmetic logic unit (ALU) performs arithmetic operations such as addition and subtraction and logic operations such as AND, OR, and NOT.
Looking at the system, the CPU is connected to the rest of the computer via pins attached to the CPU socket in the computer’s motherboard. Most of the pins on the CPU are connected to the data bus, the control bus, and the address bus. The memory storage unit is where instructions and data are temporarily stored while a computer program is running. The storage unit receives a request for data from the CPU, then transfers all data stored from random access memory (RAM) to the CPU, and finally transfers data from the CPU into memory. All the processing of data takes place within the CPU, so programs that exist in memory must be copied into the CPU before they can execute any commands. Individual program instructions or functions can be copied into the CPU one at time, or groups can be copied together at the same time.
A bus is a group of parallel wires that transfer data from one part of the computer system to another. A computer system usually contains four bus types: data, input & output (I/O), control, and address. The data bus transfers instructions and data between the CPU and memory. The I/O bus transfers data between the CPU and the devices in the computer system that have input/output commands. The control bus utilizes binary signals to synchronize actions of any device that is connected the system bus. Lastly, the address bus holds the addresses of instructions and data when the currently executing instruction transfers data between the CPU and memory. Below is an illustration of the block diagram of a Microcomputer.
Instruction Execution Cycle
The execution of a single machine instruction can be separated into a sequence of individual operations called the instruction execution cycle. Before any executions can occur, a program is loaded into memory. The instruction pointer contains the address of the next instruction to be executed. When executing a machine’s instructions, three basic steps are required: fetch, decode, and execute. Two more steps are required if the instruction is using a memory operand: fetch operand and output operand. Each of the steps can be described as follows:
Fetch: The control unit fetches the next execution instruction from the instruction and increments the instruction pointer (IP). The IP is known as the program counter.
Decode: The control unit decodes the instruction’s function to determine what the instruction will do. The instruction’s input operands are passed to the ALU, and signals are sent to the LAU indicating the operation to be performed.
Fetch operands: If the instruction uses an input operand located in memory, the CU uses a read operation to retrieve the operand and copy it into internal registers. Internal registers are not visible to any user programs.
Execute: The ALU executes the instruction using the named registers and internal registers as operands and sends the output to named registers and/or memory.
Store output operand: If the output operand is in the memory, the CU uses the write operation to store the data.
Below is a diagram to help show relationships between components that interact during the instruction execution cycle. If program instructions are to be read from memory, an address is placed on the address bus. Next, the memory controller places the requested code on the data bus, allow the code to be available inside the code cache. The instruction pointer’s value determines which program instruction will execute next. The instruction is analyzed by the instruction decode, causing the appropriate digital signals to be sent to the control unit, which coordinates the ALU and floating-point unit. The control bus is not shown in the figure, but it carries various signals that use the system clock to coordinate the transfer of data between the different CPU components.
Reading from Memory
Program throughput is frequently dependent on the speed of the memory access. CPU clock speed could be eight gigahertz, whereas the access to memory occurs over a system bus running at a much slower speed than that of the clock’s speed. The CPU must wait one or more clock cycles until operands have been fetched from memory before the current instruction can complete its full execution. The wasted clock cycles are known as wait states.
Several steps are required when reading instructions or data from memory, controlled by the processor’s clock. The diagram below depicts the processor clock (CLK) rising and falling at regular time intervals. In this figure, the clock cycle begins as soon as the clock signal changes from high to low (1 to 0). These changes are known as trailing edges, and they indicate the time taken by the transition between every state.
Below is a reduced description of what happens during each clock cycle when the memory is read:
Cycle 1: The address bits of the memory operand are placed on the address bus (ADDR). The address lines in the diagram cross, showing that some bits equal 1 and others equal 0.
Cycle 2: The read line (RD) is set low (o) to inform memory that a value is to be read.
Cycle 3: The CPU waits one cycle to give memory time to respond. During this period, the memory controller places the operand on the data bus (DATA).
Cycle 4: The read line goes to 1, signaling the CPU to read the data on the data bus.
At this point, you should have a basic understanding of x86 processor architecture fundamentals as they operate a computer system. Future articles will focus on x86 architecture details such as how programs run and multitasking. Other topics that will be detailed are modes of operation execution environments, execution registers, and x86 memory management will be provided for you to understand and improve your x86 processor knowledge.
Next Article in Series: x86 Architecture: Processes and Execution Environments