The Bluetooth LE 5 specification is the latest iteration of the BluetoothLE standard and includes new physical layer (PHY) specifications that allow increased speed (x2) or increased range (x4.) This technical article looks at the bit data paths of the three different variants, LE 1M, LE 2M, and LE 1M Coded.


The following article takes technical information from the Bluetooth 5 Core Specification and presents it in abridged form. Since excessive quotation marks adversely affect the readability of the article, attribution is provided in the form of a page-number reference in the Core Specification. The file at the end of this section contains the full 2822 page Bluetooth Specification Version 5.0 used as a reference in this article. For the latest changes and improvements visit



The lowest level of the Open Systems Interconnection (OSI) model is the physical layer, often simply referred to as PHY. In wireless semiconductors, this is the part of the circuitry where bits are converted to radio signals and then back to bits on a remote device. 

BLE5 created two new PHY implementations that allow improved performance over the Bluetooth LE 4.0 specification. The two new variants allow for increased speed or increased range without increasing the transmit power. The improvements come from improved receiver sensitivity and improved error correction, not increased transmitting power.

  • LE 1M PHY — 1 Megasymbol / second options:
    • LE 1M:  Uncoded data is transmitted at 1 Mb/s.
    • LE Coded:  Access Address, Coding Indicator, and TERM1 fields coded at 125 kb/s, and payload coded at either (s=8) 125 kb/s or (s=2) 500 kb/s2533
  • LE 2M PHY — 2 Megasymbols / second option:
    • Uncoded data is transmitted at 2 Mb/s2533


Packet Format for LE 1M Uncoded and LE 2M PHY Uncoded

Packets consist of a preamble, access address, variable length Protocol Data Unit (PDU), and a Cyclic Redundancy Check (CRC).


Link layer packet format for LE uncoded PHYs 2562



The preamble is used by the receiver to perform frequency synchronization, symbol timing estimation, and automatic gain control training. For the uncoded LE 1M and 2M PHYs, it consists of an alternating sequence of 0 and 1, where the first bit is equal to the LSB of the access address.2562


Access Address

The Access Address (AA) value is set in the SyncInfo field during advertising or is set to 0x8E89BED6. Each Link Layer connection between any two devices and each periodic advertisement has a different Access Address.2563



The Protocol Data Unit (PDU) follows the Access Address. If the packet is on the primary or secondary advertising channel, it will be the Advertising Channel PDU. If the packet is transmitted on a data channel, the PDU shall be a Data Channel PDU.2564  PDU format is not covered in this article, to learn more about the PDUs see pages 2567 and 2587.



A 24 bit (3 Octet) Cyclic Redundancy Check (CRC) is calculated with the bits from the PDU 2564. It is transmitted at the end of the packet.


Packet Format for LE 1M Coded PHY

Each Packet consists of an uncoded preamble, FEC Block 1, and FEC Block 2.2565


Link Layer Packet Format for the LE 1M Coded PHY2565



The preamble is uncoded and consists of 10 repetitions of 0x3C (001111002)


FEC Block 1

Access Address

The access address is set in the SyncInfo field during advertisement or is set to 0x8E89BED6.


Coding Indication

The coding indicator consists of two bits, 002 indicates that FEC Block 2 is encoded using S=8, and 012 indicates that FEC Block 2 is encoded using S=2. The FEC encoder generates two output bits for every one input bit. When used, the pattern encoder generates four output bits for every one input bit. S=2 indicates that the number of bits is doubled after leaving the FEC encoder. S=8 indicates that the input bits are doubled in the FEC encoder, and those bits are then quadrupled by the Pattern Encoder $$1 \; \text{bit}\times \underset{\text{FEC}}{\frac{2\;\text{bits}}{1\;\text{bit}}} \times \underset{\text{Pattern}}{\frac{4\;\text{bits}}{1\;\text{bit}}}$$



Three consecutive zeros indicate a termination sequence and reset the FEC encoder (0002).


FEC Block 2

Everything in FEC Block 2 is encoded according to the Coding Indicator in Block 1.



The Protocol Date Unit is either the Advertising Channel PDU or the Data Channel PDU. Before encoding, the data length ranges between 16 and 2056 bits. After encoding, the range becomes either 128 - 16448 bits (S=8) or 32 - 4112 bits (S=2).



The 24 bit (3 Octet) Cyclic Redundancy Check (CRC) is calculated with the bits from the PDU 2564. It is transmitted at the end of the packet.



Three consecutive zeros terminate the transmission and reset the FEC encoder (0002).


  BLE 5 Core Specification  

Most Bluetooth LE 5 devices will remain backwards-compatible with Bluetooth LE 4 devices. To take advantage of new features, you will need two BLE5 capable devices. You will not see the increased range or data rate unless both devices are BLE 5 compatible.

Depending on the PHY used data takes one of two paths. Both paths encrypt the data with Advanced Encryption Standard - Counter with CBC MAC (AES-CCM, where CBC-MAC is the initialism for Cipher Block Chaining Message Authentication Code.) After encryption, data is sent through a Cyclic Redundancy Check (CRC) algorithm, and then a Data Whitening algorithm to prevent long strings of 0's and 1's. If you are using LE coded, data is then sent through a Forward Error Correction (FEC) encoder and a Pattern mapper. Data is then broadcast through the air.


Bit data path for LE 1M and LE 2M unencoded data


Bit data path for LE coded


Received packets go through the same processes as the transmitted packets but in reverse order.


Cyclic Redundancy Check


The cyclic redundancy check is performed on the Protocol Data Unit (PDU) field in all link layer packets. If the PDU is encrypted, the CRC is calculated after encryption. The CRC polynomial is a 24-bit polynomial x24+x10+x9+x6+x4+x3+x1+x0 that corresponds physically to a Linear Feedback Shift Register (LFSR) with XOR taps at bit 0, 1, 3, 4, 6, 9, 10, and 24.  

Data is shifted into the shift register beginning with the Least Significant Bit.2600 The shift register is initialized with a known shared value or 0x555555. 2601


Example CRC encoding in a Linear Feedback Shift Register preset with 0x555555 (010101010101010101010101). Animation by Mark Hughes


When a packet is received, the Access Address is checked followed by the CRC. If either is incorrect the packet is rejected and processing stops.2600


Data Whitening

Data whitening prevents long sequences of repetitive bits (00000000 or 11111111). It is applied to the PDU and CRC fields of all Link-Layer packets after the CRC of the transmitter. De-whitening is performed before the CRC in the receiver. Both the whitener and de-whitener use a 7-bit linear feedback shift register (LFSR) with taps at bit 4 and bit 7.  

The shift register is initialized with a sequence that is derived from the channel index. Position 0 is set to 1, and positions 1 to 6 are set to the channel index of the channel used when transmitting or receiving, with the MSB in position 1 and the LSB in position 62601.

Bits are shifted along the shift register from 0→1, 1→2, 2→3, 4→5, 5→6, 6→0.  Bit 3 and bit 6 are processed with the XOR ⊕ operator to determine bit 4 (0⊕0=0,0⊕1=1,1⊕0=1,1⊕1=0)


Image illustrating logic inside the data whitening linear feedback shift register initialized with channel 19 (010011). Animation by Mark Hughes



Data is encoded by a convolutional Forward Error Correction encoder and then sent to a pattern mapper.


Convolutional Encoder

Data is shifted to a non-systematic, non-recursive, 1/2 rate, convolutional forward-error-correction (FEC) encoder with constraint length K=4.2602  Each input bit generates two output bits by repetitively adding the input bit and bits previously stored in the register with the XOR operator.  The initial state and termination sequence of the encoder is three consecutive zeros.  


The animation above shows input bits fed into a convolutional forward error correction encoder to produce two output bits, doubling the characters. Animation by Mark Hughes.


The data that entered the FEC "01101111010110000" becomes "001101011110100110110100100100".  The extra data allows a decoding algorithm to correct a single incorrect bit, and detect two consecutive incorrect bits.


Pattern Mapper

Two pattern mapper options are available, P=1 (used by S=2) and P=4 (used by S=8.)  The P=1 mapper produces an output bit that is identical to the input bit.  The P=4 mapper produces the four output bits 0011 when the input bit is 0, and the four output bits 1100 when the input bit is 1.


Input Bit Output


0 0 0011
1 1 1100


The sequence that left the convolutional forward error correction encoder "00110101" will stay "00110101" when P=1 (S=2), or become "0011 0011 1100 1100 0011 1100 1100 1100 1100" when P=4.  


Data Reception

As bits arrive at the receiver, extraneous electromagnetic energy in the vicinity of the receiver can cause bits to be incorrectly detected.  For the LE 1M Coded PHY, the additional bits provided by the pattern encoder and additional data provided by the Forward Error Correction encoder allow the decoding algorithm to correct multiple bit errors, but the increase in the number of symbols decreases the overall throughput.  


Four octets of data with errors.


 Since the pattern map is known (0 = 0011 and 1 = 1100), a certain number of incorrect bits can be immediately corrected.


Four octets of data with errors corrected.


Even if the pattern decoder is unable to correct the bits, the extra information encoded by the forward error correction encoder allows detection and correction of a certain number of incorrectly deciphered bits.  Individual bits that are shifted into the Forward Error Correction encoder change the internal state of the shift registers.  Each current state of the shift register can transition to only one of two other states (not the full eight.)

Each circle above shows the values stored in one state of the shift register and the path to the next allowed states. New input bits (0 or 1) that shift in from the left determine the next allowed state.


By knowing the output bits and the allowed state path of the shift register, the decoder can predict the current and past state of the shift register, and then use that information to determine the original input bits.

To learn more about FEC encoding and decoding, the Viterbi algorithm, and Trellis Diagrams, refer to Design Note ND504 from Texas Instruments.



The new PHY layers of the Bluetooth 5 specification allow for either high-speed (2x) or long-distance (4x) BLE connectivity. These PHYs bring greater functionality to the already ubiquitous BluetoothLE standard and will undoubtedly change the way we use the next generation of LE devices.

The preceding article takes technical information in abridged form from the Bluetooth 5 Core Specification—attribution is provided in the form of a page-number reference to the Core Specification document.


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