Simulating SiC MOSFET Thermal and Switching Behavior in LTspice
In this article, we’ll set up a basic SiC switching circuit and perform some transient simulations.
The previous article explained how to incorporate Wolfspeed’s silicon carbide (SiC) MOSFET models into LTspice and then how to add a specific device to a schematic.
Now, I’d like to discuss a few details related to these SPICE models, and then we’ll examine the switching behavior of the C2M0025120D, which is an N-channel SiC FET in a TO-247 package that can handle 90 A of continuous drain current and has a typical on-state resistance of 25 mΩ.
Electrothermal SPICE Models
The SPICE models that we’re using in this series are pretty typical with regard to electrical behavior, but Wolfspeed has incorporated some interesting temperature-related features that are, in my experience, quite uncommon. Let’s take another look at the circuit that I presented at the end of the previous article:
As expected, we have gate, drain, and source terminals, but what are those Tj and Tc connections?
Those are “terminals” for the junction temperature and case temperature, and they introduce some valuable functionality into these models. The idea here is that temperature is monitored and controlled as though it were a voltage, such that we can easily integrate thermal analysis and experimentation into our voltage-and-current-based SPICE simulations. For both Tj and Tc, 1 V corresponds to 1°C.
Specifying Case Temperature
One straightforward way to use these pins is to connect Tc to a constant voltage that represents the ambient temperature and then observe how circuit operation affects Tj. In the circuit below, I’ve connected Tc to an ambient temperature of 25°C, and I’ve changed the load resistance to 2 Ω, which results in a continuous load current of about 50 A when the transistor is turned on.
Here are the long-term case and junction temperatures:
As you can see, Tc stays constant at the chosen ambient temperature. Tj is initially at the same temperature as Tc, but after the FET is switched on, high drain current results in a rapid rise in temperature. The device reaches thermal equilibrium after about 100 ms, settling on a junction temperature of 43.6°C.
An important thing to understand about junction temperature in a scenario such as this is that the value present at the Tj terminal is not merely “informational.” The electrical behavior of the SPICE model changes in response to the device’s thermal conditions, and consequently you can use the Tc pin not only to estimate junction temperature but also to explore the relationship between ambient temperature and variations in electrical performance.
Specifying Junction Temperature
By applying a voltage to the Tc terminal, you can observe how Tj changes over time. If instead you want to characterize the electrical behavior of the FET at a specific junction temperature, you can apply a voltage to the Tj terminal and leave the Tc terminal unconnected.
Applying a fixed voltage to Tj is obligatory when you’re performing a DC simulation, because the model needs to know which junction temperature it should use when calculating currents and voltages.
What If I Don’t Care about Thermal Effects?
You still have to do something with the Tc or Tj terminal. The model doesn’t work if both are left unconnected.
Simulating Switching Behavior
We can use the following simple circuit to do some basic experimentation with the use of a silicon-carbide FET for high-power switching tasks—such as motor drive, switch-mode regulation, or induction heating—that we would typically accomplish with a silicon MOSFET or IGBT.
The datasheet for the C2M0025120D recommends operational gate-source voltages of +20 V and –5 V, so I configured V2 as a square wave that swings between those two values with rise and fall times of 10 ns. Here is a plot of the gate voltage and the current through Rload.
Since the rise/fall time of the green trace is only 10 ns, we can see that the FET achieves rapid load switching: less than 65 ns for both turn-on and turn-off transitions.
As shown in the next plot, the on-state current stabilizes at about 49.2 A.
The supply voltage for the load is 100 V, so the total load-path resistance is 100 V / 49.2 A = 2.03 Ω. We have a 2 Ω load, so the on-state resistance of the SiC FET is about 30 mΩ, which is very close to the datasheet value of 25 mΩ.
Let’s conduct one quick experiment before we finish up. What happens if we change the gate-drive waveform to something much more convenient, say, 0 to 5 V instead of –5 to 20 V? The typical threshold voltage of the C2M0025120D is only 2.6 V, so the circuit should be functional. However, we expect significantly impaired performance, and as the next plot shows, that’s exactly what we get.
Now we have quite a bit of ringing on the rising edges of the load current, and the on-state resistance has increased to about 29 Ω.
We can significantly improve the on-state resistance and ringing by increasing the turn-on voltage to 10 V, but the load-current rise time is quite long:
We’ve carried out some basic simulations of silicon carbide switching behavior in a high-power application, and we also discussed the thermal-effect-related functionality of Wolfspeed’s SiC SPICE models.
If you have any ideas for useful or interesting simulations involving SiC technology, or if you’ve ever used simulations to facilitate a transition from silicon components to SiC components, let us know in the comments!