Insulated gate field-effect transistors are unipolar devices just like JFETs: that is, the controlled current does not have to cross a PN junction. There is a PN junction inside the transistor, but its only purpose is to provide that nonconducting depletion region which is used to restrict current through the channel.

Here is a diagram of an N-channel IGFET of the “depletion” type:

Notice how the source and drain leads connect to either end of the N channel, and how the gate lead attaches to a metal plate separated from the channel by a thin insulating barrier. That barrier is sometimes made from silicon dioxide (the primary chemical compound found in sand), which is a very good insulator. Due to this Metal (gate) - Oxide (barrier) - Semiconductor (channel) construction, the IGFET is sometimes referred to as a MOSFET. There are other types of IGFET construction, though, and so “IGFET” is the better descriptor for this general class of transistors.

Notice also how there are four connections to the IGFET. In practice, the substrate lead is directly connected to the source lead to make the two electrically common. Usually, this connection is made internally to the IGFET, eliminating the separate substrate connection, resulting in a three-terminal device with a slightly different schematic symbol:

With source and substrate common to each other, the N and P layers of the IGFET end up being directly connected to each other through the outside wire. This connection prevents any voltage from being impressed across the PN junction. As a result, a depletion region exists between the two materials, but it can never be expanded or collapsed. JFET operation is based on the expansion of the PN junction’s depletion region, but here in the IGFET that cannot happen, so IGFET operation must be based on a different effect.

Indeed it is, for when a controlling voltage is applied between gate and source, the conductivity of the channel is changed as a result of the depletion region moving closer to or further away from the gate. In other words, the channel’s effective width changes just as with the JFET, but this change in channel width is due to depletion region displacement rather than depletion region expansion.

In an N-channel IGFET, a controlling voltage applied positive (+) to the gate and negative (-) to the source has the effect of repelling the PN junction’s depletion region, expanding the N-type channel and increasing conductivity:

Reversing the controlling voltage’s polarity has the opposite effect, attracting the depletion region and narrowing the channel, consequently reducing channel conductivity:

The insulated gate allows for controlling voltages of any polarity without danger of forward-biasing a junction, as was the concern with JFETs. This type of IGFET, although its called a “depletion-type,” actually has the capability of having its channel either depleted (channel narrowed) or enhanced (channel expanded). Input voltage polarity determines which way the channel will be influenced.

Understanding which polarity has which effect is not as difficult as it may seem. The key is to consider the type of semiconductor doping used in the channel (N-channel or P-channel?), then relate that doping type to the side of the input voltage source connected to the channel by means of the source lead. If the IGFET is an N-channel and the input voltage is connected so that the positive (+) side is on the gate while the negative (-) side is on the source, the channel will be enhanced as extra electrons build up on the channel side of the dielectric barrier. Think, “negative (-) correlates with N-type, thus enhancing the channel with the right type of charge carrier (electrons) and making it more conductive.” Conversely, if the input voltage is connected to an N-channel IGFET the other way, so that negative (-) connects to the gate while positive (+) connects to the source, free electrons will be “robbed” from the channel as the gate-channel capacitor charges, thus depleting the channel of majority charge carriers and making it less conductive.

For P-channel IGFETs, the input voltage polarity and channel effects follow the same rule. That is to say, it takes just the opposite polarity as an N-channel IGFET to either deplete or enhance:

Illustrating the proper biasing polarities with standard IGFET symbols:

When there is zero voltage applied between gate and source, the IGFET will conduct current between source and drain, but not as much current as it would if it were enhanced by the proper gate voltage. This places the depletion-type, or simply D-type, IGFET in a category of its own in the transistor world. Bipolar junction transistors are normally-off devices: with no base current, they block any current from going through the collector. Junction field-effect transistors are normally-on devices: with zero applied gate-to-source voltage, they allow maximum drain current (actually, you can coax a JFET into greater drain currents by applying a very small forward-bias voltage between gate and source, but this should never be done in practice for risk of damaging its fragile PN junction). D-type IGFETs, however, are normally half-on devices: with no gate-to-source voltage, their conduction level is somewhere between cutoff and full saturation. Also, they will tolerate applied gate-source voltages of any polarity, the PN junction being immune from damage due to the insulating barrier and especially the direct connection between source and substrate preventing any voltage differential across the junction.

Ironically, the conduction behavior of a D-type IGFET is strikingly similar to that of an electron tube of the triode/tetrode/pentode variety. These devices were voltage-controlled current regulators that likewise allowed current through them with zero controlling voltage applied. A controlling voltage of one polarity (grid negative and cathode positive) would diminish conductivity through the tube while a voltage of the other polarity (grid positive and cathode negative) would enhance conductivity. I find it curious that one of the later transistor designs invented exhibits the same basic properties of the very first active (electronic) device.

A few SPICE analyses will demonstrate the current-regulating behavior of D-type IGFETs. First, a test with zero input voltage (gate shorted to source) and the power supply swept from 0 to 50 volts. The graph shows drain current:

n-channel igfet characteristic curve m1 1 0 0 0 mod1 vammeter 2 1 dc 0 v1 2 0 .model mod1 nmos vto=-1 .dc v1 0 50 2 .plot dc i(vammeter) .end 

As expected for any transistor, the controlled current holds steady at a regulated value over a wide range of power supply voltages. In this case, that regulated point is 10 µA (1.000E-05). Now let’s see what happens when we apply a negative voltage to the gate (with reference to the source) and sweep the power supply over the same range of 0 to 50 volts:

n-channel igfet characteristic curve m1 1 3 0 0 mod1 vin 0 3 dc 0.5 vammeter 2 1 dc 0 v1 2 0 .model mod1 nmos vto=-1 .dc v1 0 50 2 .plot dc i(vammeter) .end 

Not surprisingly, the drain current is now regulated at a lower value of 2.5 µA (down from 10 µA with zero input voltage). Now let’s apply an input voltage of the other polarity, to enhance the IGFET:

n-channel igfet characteristic curve m1 1 3 0 0 mod1 vin 3 0 dc 0.5 vammeter 2 1 dc 0 v1 2 0 .model mod1 nmos vto=-1 .dc v1 0 50 2 .plot dc i(vammeter) .end 

With the transistor enhanced by the small controlling voltage, the drain current is now at an increased value of 22.5 µA (2.250E-05). It should be apparent from these three sets of voltage and current figures that the relationship of drain current to gate-source voltage is nonlinear just as it was with the JFET. With 1/2 volt of depleting voltage, the drain current is 2.5 µA; with 0 volts input the drain current goes up to 10 µA; and with 1/2 volt of enhancing voltage, the current is at 22.5 µA. To obtain a better understanding of this nonlinearity, we can use SPICE to plot the drain current over a range of input voltage values, sweeping from a negative (depleting) figure to a positive (enhancing) figure, maintaining the power supply voltage of V1 at a constant value:

n-channel igfet m1 1 3 0 0 mod1 vin 3 0 vammeter 2 1 dc 0 v1 2 0 dc 24 .model mod1 nmos vto=-1 .dc vin -1 1 0.1 .plot dc i(vammeter) .end 

Just as it was with JFETs, this inherent nonlinearity of the IGFET has the potential to cause distortion in an amplifier circuit, as the input signal will not be reproduced with 100 percent accuracy at the output. Also notice that a gate-source voltage of about 1 volt in the depleting direction is able to pinch off the channel so that there is virtually no drain current. D-type IGFETs, like JFETs, have a certain pinch-off voltage rating. This rating varies with the precise unique of the transistor, and may not be the same as in our simulation here.

Plotting a set of characteristic curves for the IGFET, we see a pattern not unlike that of the JFET:


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