# Design Project: Pulse-Width Modulation (PWM) Signal Generator

• #### Question 1

What shape of voltage waveform would you expect to measure (using an oscilloscope) across capacitor C1? How does this waveform interact with the DC reference voltage at the wiper of Rpot2 to produce a pulse-width modulated square wave output?

• #### Question 2

Which direction would you have to move the wiper on potentiometer Rpot2 to increase the duty cycle of the output waveform? Explain your answer.

• #### Question 3

The design recommendation for this circuit is to make resistors R2 and R3 both equal to the resistance of the potentiometer Rpot2. This way, the full mechanical range of the potentiometer will be useful for adjusting duty cycle: fully turning it one way will just produce a 0% duty cycle, while fully turning it the other way will just produce a 100% duty cycle.

Explain why those resistor values need to be equal to achieve this optimum usage of pot range. Hint: it has something to do with the internal workings of the 555 timer IC.

• #### Question 4

It is important to not make resistor R1 too small in value. Explain why, and what might happen if it were.

• #### Question 5

For those of you who are used to working with regular opamps, the presence of resistor R4 may be a mystery. It is necessary because of a special limitation of the type LM339 comparator IC. Research and explain what this limitation is.

• #### Question 6

The following modification may be made to the circuit to provide it with additional output current capability:

Here, six CMOS inverters (IC part number 4049) are ganged together in parallel to supply significantly more sourcing and sinking current capability than the LM339-with-pullup-resistor could on its own. Since CMOS logic gates are inherently on-or-off devices, they have no trouble handling the square wave output of the LM339.

Two questions here: first, why all the resistors at the outputs of the inverter gates? Why not just connect all the inverter outputs directly in parallel? Secondly, what value of resistor would you suggest at the output of each gate (R5 through R10)?